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Development of process parameters for 22 nm PMOS using 2-D analytical modeling

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology beco...

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Main Authors: Maheran, A.H.A., Menon, P.S., Ahmad, I., Shaari, S., Faizah, Z.A.N.
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Published: 2017
Online Access:http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5199
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spelling my.uniten.dspace-51992017-11-15T02:56:31Z Development of process parameters for 22 nm PMOS using 2-D analytical modeling Maheran, A.H.A. Menon, P.S. Ahmad, I. Shaari, S. Faizah, Z.A.N. The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO2) and tungsten silicide (WSix). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum ILEAK where the maximum predicted ILEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/μm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in ILEAK mean value of 3.96821 nA/μm where is far lower than the predicted value. © 2015 AIP Publishing LLC. 2017-11-15T02:56:31Z 2017-11-15T02:56:31Z 2015 http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5199
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
description The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO2) and tungsten silicide (WSix). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum ILEAK where the maximum predicted ILEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/μm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in ILEAK mean value of 3.96821 nA/μm where is far lower than the predicted value. © 2015 AIP Publishing LLC.
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author Maheran, A.H.A.
Menon, P.S.
Ahmad, I.
Shaari, S.
Faizah, Z.A.N.
spellingShingle Maheran, A.H.A.
Menon, P.S.
Ahmad, I.
Shaari, S.
Faizah, Z.A.N.
Development of process parameters for 22 nm PMOS using 2-D analytical modeling
author_facet Maheran, A.H.A.
Menon, P.S.
Ahmad, I.
Shaari, S.
Faizah, Z.A.N.
author_sort Maheran, A.H.A.
title Development of process parameters for 22 nm PMOS using 2-D analytical modeling
title_short Development of process parameters for 22 nm PMOS using 2-D analytical modeling
title_full Development of process parameters for 22 nm PMOS using 2-D analytical modeling
title_fullStr Development of process parameters for 22 nm PMOS using 2-D analytical modeling
title_full_unstemmed Development of process parameters for 22 nm PMOS using 2-D analytical modeling
title_sort development of process parameters for 22 nm pmos using 2-d analytical modeling
publishDate 2017
url http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5199
_version_ 1644493612170346496
score 13.211869

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