Vth and ILEAK Optimization using taguchi method at 32nm bilayer graphene PMOS
A 32nm top-gated bilayer Graphene PMOS transistor was optimized and analyzed to find the optimum value of performance parameters besides investigating the process parameter that affects the performance of the bilayer Graphene transistor the most. Firstly, ATHENA and ATLAS modules which can be found...
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
2017
|
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Be the first to leave a comment!