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LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage

This paper presents a low hardware overhead scan- based test pattern generator (TPG) that can reduce switching activity in circuit under test (CUT) during test and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed TPG is comprised of two TPGs: Seed selecte...

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Main Authors:	Islam S.Z., Ali M.A.M.
Other Authors:	55432804400
Format:	Conference paper
Published:	Institute of Electrical and Electronics Engineers Inc. 2023
Subjects:	Cost reduction Hardware Benchmark circuit Circuit under test Fault coverages Hardware overheads Hybrid patterns Low hardware costs Low-power dissipation Switching activities Built-in self test
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id	my.uniten.dspace-30942
record_format	dspace
spelling	my.uniten.dspace-309422023-12-29T15:56:16Z LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage Islam S.Z. Ali M.A.M. 55432804400 6507416666 Cost reduction Hardware Benchmark circuit Circuit under test Fault coverages Hardware overheads Hybrid patterns Low hardware costs Low-power dissipation Switching activities Built-in self test This paper presents a low hardware overhead scan- based test pattern generator (TPG) that can reduce switching activity in circuit under test (CUT) during test and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed TPG is comprised of two TPGs: Seed selected Random Test Pattern Generator (RTPG) and 3-weight Weighted Random Built-in-Self Test (WRBIST). Test pattern generated by seed selected RTPG detect easy-to-detect faults and test pattern generated by 3-weight WRBIST detect hard faults that remain undetected after seed selected RTPG patterns are applied. Experimental results show that the proposed TPG schemes can attain 100% fault coverage for all benchmark circuits with drastically reduced test sequence lengths. This reduction in test sequence length achieved at low hardware cost even for benchmark circuits that have large number of scan inputs. � 2008 IEEE. Final 2023-12-29T07:56:16Z 2023-12-29T07:56:16Z 2008 Conference paper 10.1109/APCCAS.2008.4746380 2-s2.0-62949244911 https://www.scopus.com/inward/record.uri?eid=2-s2.0-62949244911&doi=10.1109%2fAPCCAS.2008.4746380&partnerID=40&md5=5485713f9b62bea77c40fdb2e1c5119b https://irepository.uniten.edu.my/handle/123456789/30942 4746380 1755 1758 Institute of Electrical and Electronics Engineers Inc. Scopus
institution	Universiti Tenaga Nasional
building	UNITEN Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
url_provider	http://dspace.uniten.edu.my/
topic	Cost reduction Hardware Benchmark circuit Circuit under test Fault coverages Hardware overheads Hybrid patterns Low hardware costs Low-power dissipation Switching activities Built-in self test
spellingShingle	Cost reduction Hardware Benchmark circuit Circuit under test Fault coverages Hardware overheads Hybrid patterns Low hardware costs Low-power dissipation Switching activities Built-in self test Islam S.Z. Ali M.A.M. LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage
description	This paper presents a low hardware overhead scan- based test pattern generator (TPG) that can reduce switching activity in circuit under test (CUT) during test and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed TPG is comprised of two TPGs: Seed selected Random Test Pattern Generator (RTPG) and 3-weight Weighted Random Built-in-Self Test (WRBIST). Test pattern generated by seed selected RTPG detect easy-to-detect faults and test pattern generated by 3-weight WRBIST detect hard faults that remain undetected after seed selected RTPG patterns are applied. Experimental results show that the proposed TPG schemes can attain 100% fault coverage for all benchmark circuits with drastically reduced test sequence lengths. This reduction in test sequence length achieved at low hardware cost even for benchmark circuits that have large number of scan inputs. � 2008 IEEE.
author2	55432804400
author_facet	55432804400 Islam S.Z. Ali M.A.M.
format	Conference paper
author	Islam S.Z. Ali M.A.M.
author_sort	Islam S.Z.
title	LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage
title_short	LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage
title_full	LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage
title_fullStr	LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage
title_full_unstemmed	LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage
title_sort	lfsr based hybrid pattern scheme achieving low power dissipation and high fault coverage
publisher	Institute of Electrical and Electronics Engineers Inc.
publishDate	2023
_version_	1806426471566147584
score	13.211869

LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage

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