Staff View: Design and optimization of 22nm NMOS transistor

Design and optimization of 22nm NMOS transistor

In this paper, we investigate the effects of four process parameters and two process noise parameters on the threshold voltage (V th) of a 22nm NMOS transistor. We used TiO 2 as the high-k material to replace the SiO 2 dielectric. The NMOS transistor was simulated using the fabrication tool ATHENA a...

Full description

Saved in:

Bibliographic Details
Main Authors:	Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Majlis B.Y., Salehuddin F.
Other Authors:	36570222300
Format:	Article
Published:	2023
Subjects:	22nm NMOS ANOVA Orthogonal array Taguchi method Threshold voltage
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my.uniten.dspace-29507
record_format	dspace
spelling	my.uniten.dspace-295072023-12-28T14:30:17Z Design and optimization of 22nm NMOS transistor Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. Elgomati H.A. Majlis B.Y. Salehuddin F. 36570222300 57201289731 12792216600 6603595092 36536722700 6603071546 36239165300 22nm NMOS ANOVA Orthogonal array Taguchi method Threshold voltage In this paper, we investigate the effects of four process parameters and two process noise parameters on the threshold voltage (V th) of a 22nm NMOS transistor. We used TiO 2 as the high-k material to replace the SiO 2 dielectric. The NMOS transistor was simulated using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. Taguchi's experimental design strategy was implemented with the L9 orthogonal array for conducting 36 simulation runs. The simulators were used for computing V th values for each row of the L9 array with 4 combinations of the 2 noise factors. The objective function for minimizing the variance in V th is achieved using Taguchi's nominal-the-best signal-to-noise ratio (SNR). Analysis of Mean (ANOM) was used to determine the best settings for the process parameters whereas. Analysis of variance (ANOVA) was used to reduce the variability of Vth. The best settings were used for verification experiments and the results show V th values with the least variance and that the mean value can be adjusted to 0.306V �0.027 for the 22nm NMOS, which is well within the ITRS2011 specifications. Final 2023-12-28T06:30:17Z 2023-12-28T06:30:17Z 2012 Article 2-s2.0-84867909824 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867909824&partnerID=40&md5=1288beeeeb2cdaf1e9ef33212df51e1b https://irepository.uniten.edu.my/handle/123456789/29507 6 7 1 8 Scopus
institution	Universiti Tenaga Nasional
building	UNITEN Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
url_provider	http://dspace.uniten.edu.my/
topic	22nm NMOS ANOVA Orthogonal array Taguchi method Threshold voltage
spellingShingle	22nm NMOS ANOVA Orthogonal array Taguchi method Threshold voltage Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. Elgomati H.A. Majlis B.Y. Salehuddin F. Design and optimization of 22nm NMOS transistor
description	In this paper, we investigate the effects of four process parameters and two process noise parameters on the threshold voltage (V th) of a 22nm NMOS transistor. We used TiO 2 as the high-k material to replace the SiO 2 dielectric. The NMOS transistor was simulated using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. Taguchi's experimental design strategy was implemented with the L9 orthogonal array for conducting 36 simulation runs. The simulators were used for computing V th values for each row of the L9 array with 4 combinations of the 2 noise factors. The objective function for minimizing the variance in V th is achieved using Taguchi's nominal-the-best signal-to-noise ratio (SNR). Analysis of Mean (ANOM) was used to determine the best settings for the process parameters whereas. Analysis of variance (ANOVA) was used to reduce the variability of Vth. The best settings were used for verification experiments and the results show V th values with the least variance and that the mean value can be adjusted to 0.306V �0.027 for the 22nm NMOS, which is well within the ITRS2011 specifications.
author2	36570222300
author_facet	36570222300 Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. Elgomati H.A. Majlis B.Y. Salehuddin F.
format	Article
author	Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. Elgomati H.A. Majlis B.Y. Salehuddin F.
author_sort	Afifah Maheran A.H.
title	Design and optimization of 22nm NMOS transistor
title_short	Design and optimization of 22nm NMOS transistor
title_full	Design and optimization of 22nm NMOS transistor
title_fullStr	Design and optimization of 22nm NMOS transistor
title_full_unstemmed	Design and optimization of 22nm NMOS transistor
title_sort	design and optimization of 22nm nmos transistor
publishDate	2023
_version_	1806428510176149504
score	13.211869

Design and optimization of 22nm NMOS transistor

Similar Items