Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA
Computer architecture; Field programmable gate arrays (FPGA); Hardware; Parallel processing systems; Programmable logic controllers; Signal to noise ratio; Steganography; Wavelet transforms; Audio steganography; Dual modes; Field programmable logic; Lifting wavelet transforms; Security; Computer har...
Saved in:
Main Authors: | Shahadi H.I., Jidin R., Way W.H. |
---|---|
Other Authors: | 54956597100 |
Format: | Article |
Published: |
Elsevier Ltd
2023
|
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
High performance FPGA architecture for dual mode processor of Integer Haar Lifting-based Wavelet Transform
by: Shahadi H.I., et al.
Published: (2023) -
Lossless audio steganography based on lifting wavelet transform and dynamic stego key
by: Shahadi H.I., et al.
Published: (2023) -
A novel and high capacity audio steganography algorithm based on adaptive data embedding positions
by: Shahadi H.I., et al.
Published: (2023) -
High capacity and inaudibility audio steganography scheme
by: Shahadi H.I., et al.
Published: (2023) -
Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms
by: Sirkunan, J., et al.
Published: (2017)