Hardware Implementation of an Optimized Processor Architecture for SOBEL Image Edge Detection Operator
This paper presents an implementation of a dedicated processor for image edge detection on field programmable gate arrays (FPGAs). The processor architecture is originally a Sobel based edge detection filter optimized to minimize memory utilization, redundant calculations and hence, overall logic re...
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| Format: | Conference or Workshop Item |
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2010
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| Online Access: | http://eprints.utp.edu.my/4235/1/icias-zahraa.pdf%3Fattachauth%3DANoY7crGR_WIYeVabAL__dLRXvdX42BGyBR4YsQ9Kkx6IwE8CDbXtNR7_0B_ZTgvdQGBS4SOvZFnup4DYCRrKwVdBQDpkxCwTpPqxN0UBWC3qDBZtA0dFY_NPY_dOzLFSa8s1EK1SNOH2pIE_su-IOue63oC2sz7OYRD1gJpUHOQDPUlyNxbDAH186cC76O_g8YrPrRtGEjq%26attredirects%3D0 http://www.utp.edu.my/icias2010/ http://eprints.utp.edu.my/4235/ |
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http://eprints.utp.edu.my/4235/1/icias-zahraa.pdf%3Fattachauth%3DANoY7crGR_WIYeVabAL__dLRXvdX42BGyBR4YsQ9Kkx6IwE8CDbXtNR7_0B_ZTgvdQGBS4SOvZFnup4DYCRrKwVdBQDpkxCwTpPqxN0UBWC3qDBZtA0dFY_NPY_dOzLFSa8s1EK1SNOH2pIE_su-IOue63oC2sz7OYRD1gJpUHOQDPUlyNxbDAH186cC76O_g8YrPrRtGEjq%26attredirects%3D0http://www.utp.edu.my/icias2010/
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