Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method
This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabricat...
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Institute of Electrical and Electronics Engineers Inc.
2023
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my.uniten.dspace-218512023-05-16T10:45:42Z Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method Maheran A.H.A. Menon P.S. Shaari S. Kalaivani T. Ahmad I. Faizah Z.A.N. Apte P.R. 36570222300 57201289731 6603595092 56989358500 12792216600 56395444600 55725529100 This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (Vth). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO2/Poly-Si technology. For this, Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate. The simulation results show that the optimal threshold voltage (Vth) of -0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work. © 2014 IEEE. Final 2023-05-16T02:45:42Z 2023-05-16T02:45:42Z 2014 Conference Paper 10.1109/SMELEC.2014.6920825 2-s2.0-84908224581 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84908224581&doi=10.1109%2fSMELEC.2014.6920825&partnerID=40&md5=511aa1478155e5ad91939e558888bd29 https://irepository.uniten.edu.my/handle/123456789/21851 6920825 178 181 Institute of Electrical and Electronics Engineers Inc. Scopus |
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This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (Vth). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO2/Poly-Si technology. For this, Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate. The simulation results show that the optimal threshold voltage (Vth) of -0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work. © 2014 IEEE. |
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36570222300 |
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36570222300 Maheran A.H.A. Menon P.S. Shaari S. Kalaivani T. Ahmad I. Faizah Z.A.N. Apte P.R. |
| format |
Conference Paper |
| author |
Maheran A.H.A. Menon P.S. Shaari S. Kalaivani T. Ahmad I. Faizah Z.A.N. Apte P.R. |
| spellingShingle |
Maheran A.H.A. Menon P.S. Shaari S. Kalaivani T. Ahmad I. Faizah Z.A.N. Apte P.R. Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method |
| author_sort |
Maheran A.H.A. |
| title |
Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method |
| title_short |
Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method |
| title_full |
Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method |
| title_fullStr |
Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method |
| title_full_unstemmed |
Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method |
| title_sort |
effect of process parameter variability on the threshold voltage of downscaled 22nm pmos using taguchi method |
| publisher |
Institute of Electrical and Electronics Engineers Inc. |
| publishDate |
2023 |
| _version_ |
1806427890292621312 |
| score |
13.211869 |