Threshold voltage optimization in a 22nm High-k/Salicide PMOS device
In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | |
| Published: |
2017
|
| Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5213 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|