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Design CMOS Memristor-Based Logic Gates

As CMOS technology is continually being scaled down to its physical boundaries, it is facing difficulties such as improving saturated efficiency, increasing leakage power, and increasing power consumption. To eradicate these problems, this project proposes to use one of the most promising alternativ...

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Main Author: Nur Aini Binti Samsudin
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Language:English
Published: 2023
Subjects:
Memristor
Logic
Gates
MRL
LTspice
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spelling my.uniten.dspace-205572023-05-04T13:38:08Z Design CMOS Memristor-Based Logic Gates Nur Aini Binti Samsudin Memristor Logic Gates MRL LTspice As CMOS technology is continually being scaled down to its physical boundaries, it is facing difficulties such as improving saturated efficiency, increasing leakage power, and increasing power consumption. To eradicate these problems, this project proposes to use one of the most promising alternatives to transistors-namely the ―Memristor‖. Tha main objective of this project is to design CMOS-memristor logic gates using 0.18 micron technology. In this project, several logic gates (OR, NOR, AND, NAND, XOR, XNOR) and subtractor circuits are designed, simulated, tested and compared with traditional static CMOS approach. For the implementation of basic logic gates, the University of Michigan Memristor Model is used. For the construction of logic gates, Memristor Ratioed Logic is used. The simulation results are verified with each component truth table. Transistors will be used in conjunction with memristors for amplification where required. Half Subtractor and Full Subtractor are built out of memristor-transistor hybrid logic gates will then be simulated through LTspice software. Power dissipation and glitches can be completely eliminated by adding BUFFERs after each successive hybrid memristor-CMOS logic state. The reduction in the number of transistors per logic gate will cause a marked decrease in both size and power consumption of the resulting device. It will be compatible with conventional computer architectures to enhance the feasibility of use in present day circuits. 2023-05-03T15:05:29Z 2023-05-03T15:05:29Z 2019-10 https://irepository.uniten.edu.my/handle/123456789/20557 en application/pdf
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
language English
topic Memristor
Logic
Gates
MRL
LTspice
spellingShingle Memristor
Logic
Gates
MRL
LTspice
Nur Aini Binti Samsudin
Design CMOS Memristor-Based Logic Gates
description As CMOS technology is continually being scaled down to its physical boundaries, it is facing difficulties such as improving saturated efficiency, increasing leakage power, and increasing power consumption. To eradicate these problems, this project proposes to use one of the most promising alternatives to transistors-namely the ―Memristor‖. Tha main objective of this project is to design CMOS-memristor logic gates using 0.18 micron technology. In this project, several logic gates (OR, NOR, AND, NAND, XOR, XNOR) and subtractor circuits are designed, simulated, tested and compared with traditional static CMOS approach. For the implementation of basic logic gates, the University of Michigan Memristor Model is used. For the construction of logic gates, Memristor Ratioed Logic is used. The simulation results are verified with each component truth table. Transistors will be used in conjunction with memristors for amplification where required. Half Subtractor and Full Subtractor are built out of memristor-transistor hybrid logic gates will then be simulated through LTspice software. Power dissipation and glitches can be completely eliminated by adding BUFFERs after each successive hybrid memristor-CMOS logic state. The reduction in the number of transistors per logic gate will cause a marked decrease in both size and power consumption of the resulting device. It will be compatible with conventional computer architectures to enhance the feasibility of use in present day circuits.
format
author Nur Aini Binti Samsudin
author_facet Nur Aini Binti Samsudin
author_sort Nur Aini Binti Samsudin
title Design CMOS Memristor-Based Logic Gates
title_short Design CMOS Memristor-Based Logic Gates
title_full Design CMOS Memristor-Based Logic Gates
title_fullStr Design CMOS Memristor-Based Logic Gates
title_full_unstemmed Design CMOS Memristor-Based Logic Gates
title_sort design cmos memristor-based logic gates
publishDate 2023
_version_ 1806423991847485440
score 13.222552

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