Design CMOS Memristor-Based Logic Gates
As CMOS technology is continually being scaled down to its physical boundaries, it is facing difficulties such as improving saturated efficiency, increasing leakage power, and increasing power consumption. To eradicate these problems, this project proposes to use one of the most promising alternativ...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | |
| 語言: | English |
| 出版: |
2023
|
| 主題: | |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
| 總結: | As CMOS technology is continually being scaled down to its physical boundaries, it is facing difficulties such as improving saturated efficiency, increasing leakage power, and increasing power consumption. To eradicate these problems, this project proposes to use one of the most promising alternatives to transistors-namely the ―Memristor‖. Tha main objective of this project is to design CMOS-memristor logic gates using 0.18 micron technology. In this project, several logic gates (OR, NOR, AND, NAND, XOR, XNOR) and subtractor circuits are designed, simulated, tested and compared with traditional static CMOS approach. For the implementation of basic logic gates, the University of Michigan Memristor Model is used. For the construction of logic gates, Memristor Ratioed Logic is used. The simulation results are verified with each component truth table. Transistors will be used in conjunction with memristors for amplification where required. Half Subtractor and Full Subtractor are built out of memristor-transistor hybrid logic gates will then be simulated through LTspice software. Power dissipation and glitches can be completely eliminated by adding BUFFERs after each successive hybrid memristor-CMOS logic state. The reduction in the number of transistors per logic gate will cause a marked decrease in both size and power consumption of the resulting device. It will be compatible with conventional computer architectures to enhance the feasibility of use in present day circuits. |
|---|