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Network Partitioning & IP Placement in Network-on-Chip (NoC) :M/M/1/B Markov Chain Modelling

Among the hardest problem in Networks-on-Chip (NoC) design is to customize the topological structure of the on-chip network in order to fulfill application demand on minimal possible cost. The area cost of NoC is cut down by using Network Partitioning methods where it splits the large network into s...

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Main Author: Asrani, Lit
Format: Book
Language:English
Published: LAP LAMBERT Academic Publishing 2012
Subjects:
QA75 Electronic computers. Computer science
Online Access:http://ir.unimas.my/id/eprint/41651/1/Network%20Partitioning%20%26%20IP%20Placement.pdf
http://ir.unimas.my/id/eprint/41651/
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spelling my.unimas.ir.416512023-11-20T08:40:13Z http://ir.unimas.my/id/eprint/41651/ Network Partitioning & IP Placement in Network-on-Chip (NoC) :M/M/1/B Markov Chain Modelling Asrani, Lit QA75 Electronic computers. Computer science Among the hardest problem in Networks-on-Chip (NoC) design is to customize the topological structure of the on-chip network in order to fulfill application demand on minimal possible cost. The area cost of NoC is cut down by using Network Partitioning methods where it splits the large network into smaller division. The enhancement in area cost is reached by trimming both router area and the number of global links. From the performance context, Multi-Level Network Partitioning offers a better solution by implemented the concept of clustering. This can be done by putting those heavily communicated cores into the same portion. Therefore, the average internode distances could be minimized. This directly imply a better performance due its to shortest path. For evaluation purpose, some performance metrics are employed which are throughputs, average queue size, probability of packet lost and waiting time. As validation, the proposed technique is experimented with various real System-on-Chip (SoC) applications as case studies. LAP LAMBERT Academic Publishing 2012-06-29 Book PeerReviewed text en http://ir.unimas.my/id/eprint/41651/1/Network%20Partitioning%20%26%20IP%20Placement.pdf Asrani, Lit (2012) Network Partitioning & IP Placement in Network-on-Chip (NoC) :M/M/1/B Markov Chain Modelling. LAP LAMBERT Academic Publishing. ISBN 978-3-659-12649-9
institution Universiti Malaysia Sarawak
building Centre for Academic Information Services (CAIS)
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Sarawak
content_source UNIMAS Institutional Repository
url_provider http://ir.unimas.my/
language English
topic QA75 Electronic computers. Computer science
spellingShingle QA75 Electronic computers. Computer science
Asrani, Lit
Network Partitioning & IP Placement in Network-on-Chip (NoC) :M/M/1/B Markov Chain Modelling
description Among the hardest problem in Networks-on-Chip (NoC) design is to customize the topological structure of the on-chip network in order to fulfill application demand on minimal possible cost. The area cost of NoC is cut down by using Network Partitioning methods where it splits the large network into smaller division. The enhancement in area cost is reached by trimming both router area and the number of global links. From the performance context, Multi-Level Network Partitioning offers a better solution by implemented the concept of clustering. This can be done by putting those heavily communicated cores into the same portion. Therefore, the average internode distances could be minimized. This directly imply a better performance due its to shortest path. For evaluation purpose, some performance metrics are employed which are throughputs, average queue size, probability of packet lost and waiting time. As validation, the proposed technique is experimented with various real System-on-Chip (SoC) applications as case studies.
format Book
author Asrani, Lit
author_facet Asrani, Lit
author_sort Asrani, Lit
title Network Partitioning & IP Placement in Network-on-Chip (NoC) :M/M/1/B Markov Chain Modelling
title_short Network Partitioning & IP Placement in Network-on-Chip (NoC) :M/M/1/B Markov Chain Modelling
title_full Network Partitioning & IP Placement in Network-on-Chip (NoC) :M/M/1/B Markov Chain Modelling
title_fullStr Network Partitioning & IP Placement in Network-on-Chip (NoC) :M/M/1/B Markov Chain Modelling
title_full_unstemmed Network Partitioning & IP Placement in Network-on-Chip (NoC) :M/M/1/B Markov Chain Modelling
title_sort network partitioning & ip placement in network-on-chip (noc) :m/m/1/b markov chain modelling
publisher LAP LAMBERT Academic Publishing
publishDate 2012
url http://ir.unimas.my/id/eprint/41651/1/Network%20Partitioning%20%26%20IP%20Placement.pdf
http://ir.unimas.my/id/eprint/41651/
_version_ 1783883546394361856
score 13.211869

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