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Power Optimization for Mesh Network-on-Chip Architecture: Multilevel Network Partitioning Approach

This paper presents a power optimization for mesh Network-on-Chip (NoC) architecture by using Multilevel Network Partitioning approach. Power consumption is reduced by re-dividing the large networks into few smaller partitions. This approach assigns excessively communicated Intellectual Property (IP...

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Bibliographic Details
Main Authors: Asrani, Lit, Siti Kudnie, Sahari, R., Spawi, Shamsiah, Suhaili, Dayang Nur Salmi Dharmiza, Awang Salleh, Ana Sakura, Zainal Abidin, A. F., Hassan
Format: Proceeding
Language:English
Published: 2013
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://ir.unimas.my/id/eprint/41635/1/Power_Optimization_for_Mesh_Network_on_C.pdf
http://ir.unimas.my/id/eprint/41635/
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http://ir.unimas.my/id/eprint/41635/1/Power_Optimization_for_Mesh_Network_on_C.pdf
http://ir.unimas.my/id/eprint/41635/

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