SOFT ERROR DETECTION IN ADDER SYSTEM
Soft error can be simplified as a disruption that occurred in the circuit. Soft error can cause a malfunction in the whole digital system. The common source of soft error is caused by radiation and due to a charged particle strike at a sensitive node. It also can be called as Single Error Upse...
保存先:
| 第一著者: | |
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| フォーマット: | Final Year Project Report |
| 言語: | English English |
| 出版事項: |
Universiti Malaysia Sarawak
2022
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| 主題: | |
| オンライン･アクセス: | http://ir.unimas.my/id/eprint/39462/1/Nur%20Aisya%20Jasmin%20binti%20Mazlan%20-%20%2024pages.pdf http://ir.unimas.my/id/eprint/39462/2/Nur%20Aisya%20Jasmin%20binti%20Mazlan-%20fulltext.pdf http://ir.unimas.my/id/eprint/39462/ |
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| 要約: | Soft error can be simplified as a disruption that occurred in the circuit. Soft error can
cause a malfunction in the whole digital system. The common source of soft error is
caused by radiation and due to a charged particle strike at a sensitive node. It also can be
called as Single Error Upset (SEU). The reliability of the digital system was disrupted
and reduce because of this event. By conducting this project, the error will be detected in
different configuration of circuit with the existence of adder system and c-element by
using a logic gate. The adder system that will be used for this project is 8-bits Kogge�Stone Adder. Through this project, the configuration of the circuit will be designed, and
the results will be compared and analysed one by one in order to get the desired result.
An error will be injected into the circuit in order to imitate the soft error event that can
occurred in the system. The error will try to be detected later by using logic gates. Each
of the results will be analysed and recorded. By using Quartus Altera design software,
this project can be conducted properly, and the circuits can be designed as what has been
proposed. |
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