Design of buffer to drive large capacitive load with minimum delay
The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | Final Year Project Report |
| 語言: | English |
| 出版: |
University Malaysia Sarawak, UNIMAS.
2004
|
| 主題: | |
| 在線閱讀: | http://ir.unimas.my/id/eprint/2805/1/Khadijah%20Usaini%20ft.pdf http://ir.unimas.my/id/eprint/2805/ |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|