Design of buffer to drive large capacitive load with minimum delay
The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W...
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| 第一著者: | |
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| フォーマット: | Final Year Project Report |
| 言語: | English |
| 出版事項: |
University Malaysia Sarawak, UNIMAS.
2004
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| 主題: | |
| オンライン･アクセス: | http://ir.unimas.my/id/eprint/2805/1/Khadijah%20Usaini%20ft.pdf http://ir.unimas.my/id/eprint/2805/ |
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| 要約: | The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W than the previous by a factor of stage ration, A. |
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