Design of buffer to drive large capacitive load with minimum delay
The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | Final Year Project Report |
| 語言: | English |
| 出版: |
University Malaysia Sarawak, UNIMAS.
2004
|
| 主題: | |
| 在線閱讀: | http://ir.unimas.my/id/eprint/2805/1/Khadijah%20Usaini%20ft.pdf http://ir.unimas.my/id/eprint/2805/ |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
| id |
my.unimas.ir.2805 |
|---|---|
| record_format |
eprints |
| spelling |
my.unimas.ir.28052023-10-26T07:40:58Z http://ir.unimas.my/id/eprint/2805/ Design of buffer to drive large capacitive load with minimum delay Khadijah binti, Usaini TJ Mechanical engineering and machinery TK Electrical engineering. Electronics Nuclear engineering The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W than the previous by a factor of stage ration, A. University Malaysia Sarawak, UNIMAS. 2004 Final Year Project Report NonPeerReviewed text en http://ir.unimas.my/id/eprint/2805/1/Khadijah%20Usaini%20ft.pdf Khadijah binti, Usaini (2004) Design of buffer to drive large capacitive load with minimum delay. [Final Year Project Report] (Unpublished) |
| institution |
Universiti Malaysia Sarawak |
| building |
Centre for Academic Information Services (CAIS) |
| collection |
Institutional Repository |
| continent |
Asia |
| country |
Malaysia |
| content_provider |
Universiti Malaysia Sarawak |
| content_source |
UNIMAS Institutional Repository |
| url_provider |
http://ir.unimas.my/ |
| language |
English |
| topic |
TJ Mechanical engineering and machinery TK Electrical engineering. Electronics Nuclear engineering |
| spellingShingle |
TJ Mechanical engineering and machinery TK Electrical engineering. Electronics Nuclear engineering Khadijah binti, Usaini Design of buffer to drive large capacitive load with minimum delay |
| description |
The intention of this project is to design a cascade of inverters, known as buffer to drive a large capacitance load with a minimum delay. When moving toward the load, the delay time can be significantly reduced by cascading N numbers of inverters. Each inverter for each stage is larger by width, W than the previous by a factor of stage ration, A. |
| format |
Final Year Project Report |
| author |
Khadijah binti, Usaini |
| author_facet |
Khadijah binti, Usaini |
| author_sort |
Khadijah binti, Usaini |
| title |
Design of buffer to drive large capacitive load with minimum delay |
| title_short |
Design of buffer to drive large capacitive load with minimum delay |
| title_full |
Design of buffer to drive large capacitive load with minimum delay |
| title_fullStr |
Design of buffer to drive large capacitive load with minimum delay |
| title_full_unstemmed |
Design of buffer to drive large capacitive load with minimum delay |
| title_sort |
design of buffer to drive large capacitive load with minimum delay |
| publisher |
University Malaysia Sarawak, UNIMAS. |
| publishDate |
2004 |
| url |
http://ir.unimas.my/id/eprint/2805/1/Khadijah%20Usaini%20ft.pdf http://ir.unimas.my/id/eprint/2805/ |
| _version_ |
1781710273906737152 |
| score |
13.250246 |