Cover Image

Evaluating NoC and WiNoC Architectures for Multicore Architecture Performance

To mitigate potential scalability challenges in future many-core architectures’ on-chip communication systems, the wireless Network-on-Chip (WiNoC) design concept has arisen as a compelling choice. It offers a viable approach to address these issues effectively. This paper delves into an extensive...

Full description

Saved in:
Bibliographic Details
Main Authors: Asrani, Lit, Nazreen, Junaidi, Shamsiah, Suhaili, Shirley, Rufus, Nor Asrina, Ramlee, Fariza, Mahyan
Format: Proceeding
Language:English
Published: IEEE 2024
Subjects:
Q Science (General)
T Technology (General)
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://ir.unimas.my/id/eprint/46766/1/Evaluating_NoC_and_WiNoC_Architectures_for_Multicore_Architecture_Performance.pdf
http://ir.unimas.my/id/eprint/46766/
https://ieeexplore.ieee.org/document/10474757
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.unimas.ir-46766
record_format eprints
spelling my.unimas.ir-467662024-12-02T02:46:02Z http://ir.unimas.my/id/eprint/46766/ Evaluating NoC and WiNoC Architectures for Multicore Architecture Performance Asrani, Lit Nazreen, Junaidi Shamsiah, Suhaili Shirley, Rufus Nor Asrina, Ramlee Fariza, Mahyan Q Science (General) T Technology (General) TK Electrical engineering. Electronics Nuclear engineering To mitigate potential scalability challenges in future many-core architectures’ on-chip communication systems, the wireless Network-on-Chip (WiNoC) design concept has arisen as a compelling choice. It offers a viable approach to address these issues effectively. This paper delves into an extensive analysis of the performance evaluation concerning Network-on-Chip (NoC) and Wireless Network-on-Chip (WiNoC) configurations within the framework of a 64-core multicore system. The study encompasses a thorough evaluation across four synthetic traffic profiles, namely random, shuffle, butterfly, and transpose traffic distributions, offering a comprehensive understanding of their impact on system performance.This evaluation involved a thorough analysis of data transmission latency, the efficiency of network data throughput, and the amount of energy con-sumed. In order to substantiate our conclusions, we conducted simulations encompassing the 64-core mesh-based NoC and WiNoC architectures. These simulations were executed utilizing the Noxim simulator, a well-recognized tool acclaimed for its capacity to provide cycle-accurate simulations. Analyzing the simulation outcomes, it becomes evident that the 64-core WiNoC architecture performs better in terms of network performance. This is evident from its ability to handle heavier workloads and achieve lower delays in all traffic situations, when compared to the 64-core NoC architecture. IEEE 2024-01-01 Proceeding PeerReviewed text en http://ir.unimas.my/id/eprint/46766/1/Evaluating_NoC_and_WiNoC_Architectures_for_Multicore_Architecture_Performance.pdf Asrani, Lit and Nazreen, Junaidi and Shamsiah, Suhaili and Shirley, Rufus and Nor Asrina, Ramlee and Fariza, Mahyan (2024) Evaluating NoC and WiNoC Architectures for Multicore Architecture Performance. In: 2024 International Conference on Green Energy, Computing and Sustainable Technology (GECOST), 17-19 January 2024, Miri Sarawak, Malaysia. https://ieeexplore.ieee.org/document/10474757
institution Universiti Malaysia Sarawak
building Centre for Academic Information Services (CAIS)
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Sarawak
content_source UNIMAS Institutional Repository
url_provider http://ir.unimas.my/
language English
topic Q Science (General)
T Technology (General)
TK Electrical engineering. Electronics Nuclear engineering
spellingShingle Q Science (General)
T Technology (General)
TK Electrical engineering. Electronics Nuclear engineering
Asrani, Lit
Nazreen, Junaidi
Shamsiah, Suhaili
Shirley, Rufus
Nor Asrina, Ramlee
Fariza, Mahyan
Evaluating NoC and WiNoC Architectures for Multicore Architecture Performance
description To mitigate potential scalability challenges in future many-core architectures’ on-chip communication systems, the wireless Network-on-Chip (WiNoC) design concept has arisen as a compelling choice. It offers a viable approach to address these issues effectively. This paper delves into an extensive analysis of the performance evaluation concerning Network-on-Chip (NoC) and Wireless Network-on-Chip (WiNoC) configurations within the framework of a 64-core multicore system. The study encompasses a thorough evaluation across four synthetic traffic profiles, namely random, shuffle, butterfly, and transpose traffic distributions, offering a comprehensive understanding of their impact on system performance.This evaluation involved a thorough analysis of data transmission latency, the efficiency of network data throughput, and the amount of energy con-sumed. In order to substantiate our conclusions, we conducted simulations encompassing the 64-core mesh-based NoC and WiNoC architectures. These simulations were executed utilizing the Noxim simulator, a well-recognized tool acclaimed for its capacity to provide cycle-accurate simulations. Analyzing the simulation outcomes, it becomes evident that the 64-core WiNoC architecture performs better in terms of network performance. This is evident from its ability to handle heavier workloads and achieve lower delays in all traffic situations, when compared to the 64-core NoC architecture.
format Proceeding
author Asrani, Lit
Nazreen, Junaidi
Shamsiah, Suhaili
Shirley, Rufus
Nor Asrina, Ramlee
Fariza, Mahyan
author_facet Asrani, Lit
Nazreen, Junaidi
Shamsiah, Suhaili
Shirley, Rufus
Nor Asrina, Ramlee
Fariza, Mahyan
author_sort Asrani, Lit
title Evaluating NoC and WiNoC Architectures for Multicore Architecture Performance
title_short Evaluating NoC and WiNoC Architectures for Multicore Architecture Performance
title_full Evaluating NoC and WiNoC Architectures for Multicore Architecture Performance
title_fullStr Evaluating NoC and WiNoC Architectures for Multicore Architecture Performance
title_full_unstemmed Evaluating NoC and WiNoC Architectures for Multicore Architecture Performance
title_sort evaluating noc and winoc architectures for multicore architecture performance
publisher IEEE
publishDate 2024
url http://ir.unimas.my/id/eprint/46766/1/Evaluating_NoC_and_WiNoC_Architectures_for_Multicore_Architecture_Performance.pdf
http://ir.unimas.my/id/eprint/46766/
https://ieeexplore.ieee.org/document/10474757
_version_ 1817848778331258880
score 13.223943

Similar Items