Description: An efficient modified booth multiplier architecture

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Bibliographic Details
Main Authors:	Razaidi, Hussin, Ali Yeon, Md Shakaff, Prof. Dr., Norina, Idris, Zaliman, Sauli, Prof. Dr., Rizalafande, Che Ismail, Afzan, Kamarudin
Other Authors:	shidee@unimap.edu.my
Format:	Working Paper
Language:	English
Published:	Institute of Electrical and Electronics Engineers (IEEE) 2012
Subjects:	Booth multipliers Modified booth multipliers Multiplier architectures Architectural design Propagation delays multiplier architecture Sign extensions Transistor counts
Online Access:	http://dspace.unimap.edu.my/xmlui/handle/123456789/19693
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