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High speed 8-bits x 8-bits Wallace Tree multiplier

This final year project (FYP) is to analyze the design of Wallace Tree multiplier. For simplicity, unsigned operands are chosen and main focus on the short word widths commonly used in most applications: an 8-bit multiplier. Before this era, multiplier that used low power supply or multiplier that h...

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書目詳細資料
主要作者:	Tajul Hamimi Harun
其他作者:	Norina Idris (Advisor)
格式:	Learning Object
語言:	English
出版:	Universiti Malaysia Perlis 2008
主題:	Multipliers (Mathematical analysis) Multipliers Wallace Tree multiplier Altera Quartus II High-speed multiplier Verilog (Computer hardware description language)
在線閱讀:	http://dspace.unimap.edu.my/xmlui/handle/123456789/1937
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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