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Implementation of 128/256 bit data bus microprocessor core on FPGA

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Bibliographic Details
Main Authors:	Weng, Fook Lee, Ali Yeon, Md. Shakaff, Prof. Dr.
Other Authors:	seanlee@emersysdesign.com
Format:	Article
Language:	English
Published:	International Congress for global Science and Technology (ICGST) 2011
Subjects:	Large data bus size microprocessor VLIW FPGA
Online Access:	http://dspace.unimap.edu.my/xmlui/handle/123456789/11392
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id	my.unimap-11392
record_format	dspace
spelling	my.unimap-113922011-03-23T08:58:59Z Implementation of 128/256 bit data bus microprocessor core on FPGA Weng, Fook Lee Ali Yeon, Md. Shakaff, Prof. Dr. seanlee@emersysdesign.com aliyeon@unimap.edu.my Large data bus size microprocessor VLIW FPGA Link to publisher's homepage at http://www.icgst.com This paper shows the implementation of a large data bus size microprocessor core of 128/256 bits on an Altera Stratix 2 FPGA using a superscalar architecture of 3 parallel pipes with 4 stage pipeline as shown in Figure 1. The system level implementation utilizing the implemented microprocessor core on FPGA is shown in Figure 2. The micro-architecture of the microprocessor core architecture of Figure 1 is implemented using four pipe stages of fetch, decode, execute and writeback with a shared register file for all 3 parallel pipes, as shown in Figure 3. 2011-03-23T08:58:59Z 2011-03-23T08:58:59Z 2007-05 Article Journal of Programmable Devices, Circuits, and Systems, vol.7(1), 2007, pages 7-13 http://www.icgst.com/pdcs/Volume7/Issue1/PDCS0712001.pdf http://hdl.handle.net/123456789/11392 en International Congress for global Science and Technology (ICGST)
institution	Universiti Malaysia Perlis
building	UniMAP Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Malaysia Perlis
content_source	UniMAP Library Digital Repository
url_provider	http://dspace.unimap.edu.my/
language	English
topic	Large data bus size microprocessor VLIW FPGA
spellingShingle	Large data bus size microprocessor VLIW FPGA Weng, Fook Lee Ali Yeon, Md. Shakaff, Prof. Dr. Implementation of 128/256 bit data bus microprocessor core on FPGA
description	Link to publisher's homepage at http://www.icgst.com
author2	seanlee@emersysdesign.com
author_facet	seanlee@emersysdesign.com Weng, Fook Lee Ali Yeon, Md. Shakaff, Prof. Dr.
format	Article
author	Weng, Fook Lee Ali Yeon, Md. Shakaff, Prof. Dr.
author_sort	Weng, Fook Lee
title	Implementation of 128/256 bit data bus microprocessor core on FPGA
title_short	Implementation of 128/256 bit data bus microprocessor core on FPGA
title_full	Implementation of 128/256 bit data bus microprocessor core on FPGA
title_fullStr	Implementation of 128/256 bit data bus microprocessor core on FPGA
title_full_unstemmed	Implementation of 128/256 bit data bus microprocessor core on FPGA
title_sort	implementation of 128/256 bit data bus microprocessor core on fpga
publisher	International Congress for global Science and Technology (ICGST)
publishDate	2011
url	http://dspace.unimap.edu.my/xmlui/handle/123456789/11392
_version_	1643790173849255936
score	13.211869

Implementation of 128/256 bit data bus microprocessor core on FPGA

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