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Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results

Even though sophisticated synthesis strategies are used for optimization (e.g. area and power consumption), the quality of the result heavily depends on the quality of the Register Transfer Level (RTL). For multiplication and division by a constant number that is power of 2 can be done using left sh...

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Main Authors: Fouziah Md Yassin, Ag Asri Ag Ibrahim, Zaturrawiah Ali Omar, Saturi Baco
Format: Research Report
Language:English
Published: Universiti Malaysia Sabah 2015
Subjects:
QA Mathematics
Online Access:https://eprints.ums.edu.my/id/eprint/22892/1/Investigation%20on%20pattern%20based%20Algorithm%20for%20division%20by%20a%20constant%20number%20using%20Verilog%20code%20for%20optimization%20on%20the%20Nelust%20results.pdf
https://eprints.ums.edu.my/id/eprint/22892/
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spelling my.ums.eprints.228922019-07-22T04:34:34Z https://eprints.ums.edu.my/id/eprint/22892/ Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results Fouziah Md Yassin Ag Asri Ag Ibrahim Zaturrawiah Ali Omar Saturi Baco QA Mathematics Even though sophisticated synthesis strategies are used for optimization (e.g. area and power consumption), the quality of the result heavily depends on the quality of the Register Transfer Level (RTL). For multiplication and division by a constant number that is power of 2 can be done using left shift (multiplication) and right shift (division) in RTL design. However systems commonly multiply and divided by other constant numbers, such as by 3 or 7. An implementation of division in hardware is expensive. One of the alternatives is by replacing it with cheaper adder and shifter to compute the same result. The research is to develop an algorithm of unsigned constant division via add-shift method using Verilog code. The result is rounded to the nearest integer for divisors of 3, 5, 6, 7 and 9. The methodology of this research are involving design specification, high level design using C++, RTL level description using Verilog, functional verification and logic synthesis using two different technology library. The required results were obtained. The outputs (div_out) of all denominators (deno) have been rounded to the nearest integer. However, the maximum bit widths of numerators (numerator) are only 13 except for the divisor of 3 that has the maximum bit width up to 16. The synthesis result of area, power and timing shows the Significant difference between O.18\Jm Siltera technology and MIMOS O.351-1m technology library. However, both technologies show the optimization of power and timing for constant division using add-shift scheme. Universiti Malaysia Sabah 2015 Research Report NonPeerReviewed text en https://eprints.ums.edu.my/id/eprint/22892/1/Investigation%20on%20pattern%20based%20Algorithm%20for%20division%20by%20a%20constant%20number%20using%20Verilog%20code%20for%20optimization%20on%20the%20Nelust%20results.pdf Fouziah Md Yassin and Ag Asri Ag Ibrahim and Zaturrawiah Ali Omar and Saturi Baco (2015) Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results. (Unpublished)
institution Universiti Malaysia Sabah
building UMS Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Sabah
content_source UMS Institutional Repository
url_provider http://eprints.ums.edu.my/
language English
topic QA Mathematics
spellingShingle QA Mathematics
Fouziah Md Yassin
Ag Asri Ag Ibrahim
Zaturrawiah Ali Omar
Saturi Baco
Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results
description Even though sophisticated synthesis strategies are used for optimization (e.g. area and power consumption), the quality of the result heavily depends on the quality of the Register Transfer Level (RTL). For multiplication and division by a constant number that is power of 2 can be done using left shift (multiplication) and right shift (division) in RTL design. However systems commonly multiply and divided by other constant numbers, such as by 3 or 7. An implementation of division in hardware is expensive. One of the alternatives is by replacing it with cheaper adder and shifter to compute the same result. The research is to develop an algorithm of unsigned constant division via add-shift method using Verilog code. The result is rounded to the nearest integer for divisors of 3, 5, 6, 7 and 9. The methodology of this research are involving design specification, high level design using C++, RTL level description using Verilog, functional verification and logic synthesis using two different technology library. The required results were obtained. The outputs (div_out) of all denominators (deno) have been rounded to the nearest integer. However, the maximum bit widths of numerators (numerator) are only 13 except for the divisor of 3 that has the maximum bit width up to 16. The synthesis result of area, power and timing shows the Significant difference between O.18\Jm Siltera technology and MIMOS O.351-1m technology library. However, both technologies show the optimization of power and timing for constant division using add-shift scheme.
format Research Report
author Fouziah Md Yassin
Ag Asri Ag Ibrahim
Zaturrawiah Ali Omar
Saturi Baco
author_facet Fouziah Md Yassin
Ag Asri Ag Ibrahim
Zaturrawiah Ali Omar
Saturi Baco
author_sort Fouziah Md Yassin
title Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results
title_short Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results
title_full Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results
title_fullStr Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results
title_full_unstemmed Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results
title_sort investigation on pattern based algorithm for division by a constant number using verilog code for optimization on the nelust results
publisher Universiti Malaysia Sabah
publishDate 2015
url https://eprints.ums.edu.my/id/eprint/22892/1/Investigation%20on%20pattern%20based%20Algorithm%20for%20division%20by%20a%20constant%20number%20using%20Verilog%20code%20for%20optimization%20on%20the%20Nelust%20results.pdf
https://eprints.ums.edu.my/id/eprint/22892/
_version_ 1760230030895480832
score 13.211869

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