Selective harmonic elimination using MFO for a reduced switch multi-level inverter topology
This research article proposed a new modified single-phase multi-level inverter topology with an optimal switching control strategy to reduce the inverter output harmonic distortion. The topology is configured to operate in asymmetric mode to generate eleven levels of output voltage steps. Additiona...
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| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English English |
| Published: |
Institute of Electrical and Electronics Engineers Inc.
2022
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| Subjects: | |
| Online Access: | http://umpir.ump.edu.my/id/eprint/39411/1/Selective%20Harmonic%20Elimination%20using%20MFO%20for%20a%20Reduced%20Switch.pdf http://umpir.ump.edu.my/id/eprint/39411/2/Selective%20harmonic%20elimination%20using%20MFO%20for%20a%20reduced%20switch%20multi-level%20inverter%20topology_ABS.pdf http://umpir.ump.edu.my/id/eprint/39411/ https://doi.org/10.1109/ISIEA54517.2022.9873761 |
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