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VHDL description for IP Engine / Zeliall Bathich

Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable...

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Main Author: Zeliall, Bathich
Format: Thesis
Published: 2000
Subjects:
QA75 Electronic computers. Computer science
Online Access:http://studentsrepo.um.edu.my/9932/1/Zeliall_Bathich_%2D_Academic_exercise.pdf
http://studentsrepo.um.edu.my/9932/
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spelling my.um.stud.99322020-08-16T23:20:37Z VHDL description for IP Engine / Zeliall Bathich Zeliall, Bathich QA75 Electronic computers. Computer science Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable and reusable components. Therefore it obtains the integration of advanced tools for the development of the IP Engine into the design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of this Engine is embedded in an approach to develop flexible and configurable protocol engines that can be optimized for specific application. By implementing the IP Engine in hardware it will help reducing communication bottlenecks replacing expensive software solutions. which are based on 32 bit processor cores. With its small footprint design it will improve low power-consumption. Highly cost-effective solution to Perform all protocol functions of TCP/IP and UDP/IP connections for sustained bit rates of up to 100 Mbps independent of packet payload sizes and other connection parameters. 2000 Thesis NonPeerReviewed application/pdf http://studentsrepo.um.edu.my/9932/1/Zeliall_Bathich_%2D_Academic_exercise.pdf Zeliall, Bathich (2000) VHDL description for IP Engine / Zeliall Bathich. Undergraduates thesis, University of Malaya. http://studentsrepo.um.edu.my/9932/
institution Universiti Malaya
building UM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaya
content_source UM Student Repository
url_provider http://studentsrepo.um.edu.my/
topic QA75 Electronic computers. Computer science
spellingShingle QA75 Electronic computers. Computer science
Zeliall, Bathich
VHDL description for IP Engine / Zeliall Bathich
description Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable and reusable components. Therefore it obtains the integration of advanced tools for the development of the IP Engine into the design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of this Engine is embedded in an approach to develop flexible and configurable protocol engines that can be optimized for specific application. By implementing the IP Engine in hardware it will help reducing communication bottlenecks replacing expensive software solutions. which are based on 32 bit processor cores. With its small footprint design it will improve low power-consumption. Highly cost-effective solution to Perform all protocol functions of TCP/IP and UDP/IP connections for sustained bit rates of up to 100 Mbps independent of packet payload sizes and other connection parameters.
format Thesis
author Zeliall, Bathich
author_facet Zeliall, Bathich
author_sort Zeliall, Bathich
title VHDL description for IP Engine / Zeliall Bathich
title_short VHDL description for IP Engine / Zeliall Bathich
title_full VHDL description for IP Engine / Zeliall Bathich
title_fullStr VHDL description for IP Engine / Zeliall Bathich
title_full_unstemmed VHDL description for IP Engine / Zeliall Bathich
title_sort vhdl description for ip engine / zeliall bathich
publishDate 2000
url http://studentsrepo.um.edu.my/9932/1/Zeliall_Bathich_%2D_Academic_exercise.pdf
http://studentsrepo.um.edu.my/9932/
_version_ 1738506316546048000
score 13.211869

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