Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs
From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggre...
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| Main Authors: | , , |
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| Format: | Article |
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John Wiley & Sons
2015
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| Subjects: | |
| Online Access: | http://eprints.um.edu.my/13947/ http://onlinelibrary.wiley.com/doi/10.1002/cta.1939/abstract |
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