Multi-sized output cache controllers / Mohd Naqib Johari
This thesis describes the design of a Multi-sized Output Cache Controller that will handle 2Kbyte 16 ways with 4 word block size cache. A cache controller is a device that used to sequences the read and write of the cache storage array [1]. Most of modern microprocessor is designed with multiple cor...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2013
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| 在線閱讀: | https://ir.uitm.edu.my/id/eprint/102748/1/102748.pdf https://ir.uitm.edu.my/id/eprint/102748/ |
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