Development of interaction circuit for triple data encryption standard (3DES) using verilog for FPGA implementation / Nor Aizee Masyitah Kamal Bahrin
This report presents the development of interfacing circuit for Triple Data Encryption Standard (3DES) that is being designed using Verilog HDL for Field Programmable Gate Array (FPGA) implementation. The purpose of this project is to design the interfacing circuit that can minimize the input/output...
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| Format: | Thesis |
| Language: | English |
| Published: |
2006
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| Online Access: | https://ir.uitm.edu.my/id/eprint/102744/1/102744.pdf https://ir.uitm.edu.my/id/eprint/102744/ |
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