Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches
The current research statistics for cache designing reveals that Spin Torque Transfer Magnetic RAMs (STT-MRAMs) have become one of the most promising technologies in the field of memory chip design, gaining a lot of attention from researchers due to its dynamic direct map and data access policies...
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Main Authors: | , , , , |
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Format: | Article |
Language: | English English |
Published: |
Inderscience Publishers
2018
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Subjects: | |
Online Access: | http://irep.iium.edu.my/70884/7/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate.pdf http://irep.iium.edu.my/70884/8/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate%20SCOPUS.pdf http://irep.iium.edu.my/70884/ https://www.inderscience.com/info/inarticle.php?artid=95434 |
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Summary: | The current research statistics for cache designing reveals that Spin Torque Transfer
Magnetic RAMs (STT-MRAMs) have become one of the most promising technologies in the field of
memory chip design, gaining a lot of attention from researchers due to its dynamic direct map and data
access policies for reducing the average cost i.e. both time and energy optimisation. In this paper, the
vulnerability of STT-MRAM caches has been investigated to examine the effect of workloads as well
as process variations for characterising the reliability of STT-MRAM cache. The current study is
intended to analyse and evaluate an existing efficient cache replacement policy namely Least Error
Rate (LER) which utilises Hamming Distance (HD) computations to reduce the Write Error Rate
(WER) of L2-STT-MRAM caches with acceptable overheads. The performance analysis of the
algorithm ensures its effectiveness in reducing the WER and cost overheads as compared to the
conventional LRU techniques. |
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