A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design
In recent years, there has been a growing interest in IP-reuse for SoCs in order to bridge the gap between the silicon capacity and the design productivity. This research work investigates how our proposed methodology can be used to partition and schedule a JPEG encoder IP core onto an FPGA. We will...
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2010
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my.iium.irep.283002013-09-18T02:43:30Z http://irep.iium.edu.my/28300/ A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design Azman, Amelia Wong Bigdeli, Abbas Mohd Mustafah, Yasir Biglari-Abhari, Morteza Lovell, Brian T Technology (General) In recent years, there has been a growing interest in IP-reuse for SoCs in order to bridge the gap between the silicon capacity and the design productivity. This research work investigates how our proposed methodology can be used to partition and schedule a JPEG encoder IP core onto an FPGA. We will also describe a novel Constraint Satisfaction Problem (CSP) formulations that are used in the proposed framework. At the same time, we will also demonstrate the effectiveness of CSP in the Bayesian Network-based framework. 2010-07 Conference or Workshop Item REM application/pdf en http://irep.iium.edu.my/28300/1/A_Bayesian_network-based_framework_with_Constraint_Satisfaction_Problem_%28CSP%29_formulations_for_FPGA_system_design.pdf Azman, Amelia Wong and Bigdeli, Abbas and Mohd Mustafah, Yasir and Biglari-Abhari, Morteza and Lovell, Brian (2010) A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design. In: 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP , 7 - 9 July 2010, Rennes, France. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5540784&queryText%3D%22A+Bayesian+network-based+framework+with+Constraint+Satisfaction+Problem+%28CSP%29+formulations+for+FPGA+system+design%22 |
| institution |
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| building |
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| continent |
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| country |
Malaysia |
| content_provider |
International Islamic University Malaysia |
| content_source |
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| url_provider |
http://irep.iium.edu.my/ |
| language |
English |
| topic |
T Technology (General) |
| spellingShingle |
T Technology (General) Azman, Amelia Wong Bigdeli, Abbas Mohd Mustafah, Yasir Biglari-Abhari, Morteza Lovell, Brian A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design |
| description |
In recent years, there has been a growing interest in IP-reuse for SoCs in order to bridge the gap between the silicon capacity and the design productivity. This research work investigates how our proposed methodology can be used to partition and schedule a JPEG encoder IP core onto an FPGA. We will also describe a novel Constraint Satisfaction Problem (CSP) formulations that are used in the proposed framework. At the same time, we will also demonstrate the effectiveness of CSP in the Bayesian Network-based framework. |
| format |
Conference or Workshop Item |
| author |
Azman, Amelia Wong Bigdeli, Abbas Mohd Mustafah, Yasir Biglari-Abhari, Morteza Lovell, Brian |
| author_facet |
Azman, Amelia Wong Bigdeli, Abbas Mohd Mustafah, Yasir Biglari-Abhari, Morteza Lovell, Brian |
| author_sort |
Azman, Amelia Wong |
| title |
A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design |
| title_short |
A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design |
| title_full |
A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design |
| title_fullStr |
A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design |
| title_full_unstemmed |
A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design |
| title_sort |
bayesian network-based framework with constraint satisfaction problem (csp) formulations for fpga system design |
| publishDate |
2010 |
| url |
http://irep.iium.edu.my/28300/1/A_Bayesian_network-based_framework_with_Constraint_Satisfaction_Problem_%28CSP%29_formulations_for_FPGA_system_design.pdf http://irep.iium.edu.my/28300/ http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5540784&queryText%3D%22A+Bayesian+network-based+framework+with+Constraint+Satisfaction+Problem+%28CSP%29+formulations+for+FPGA+system+design%22 |
| _version_ |
1643609481341304832 |
| score |
13.250246 |