A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design
In recent years, there has been a growing interest in IP-reuse for SoCs in order to bridge the gap between the silicon capacity and the design productivity. This research work investigates how our proposed methodology can be used to partition and schedule a JPEG encoder IP core onto an FPGA. We will...
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| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2010
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/28300/1/A_Bayesian_network-based_framework_with_Constraint_Satisfaction_Problem_%28CSP%29_formulations_for_FPGA_system_design.pdf http://irep.iium.edu.my/28300/ http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5540784&queryText%3D%22A+Bayesian+network-based+framework+with+Constraint+Satisfaction+Problem+%28CSP%29+formulations+for+FPGA+system+design%22 |
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Internet
http://irep.iium.edu.my/28300/1/A_Bayesian_network-based_framework_with_Constraint_Satisfaction_Problem_%28CSP%29_formulations_for_FPGA_system_design.pdfhttp://irep.iium.edu.my/28300/
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5540784&queryText%3D%22A+Bayesian+network-based+framework+with+Constraint+Satisfaction+Problem+%28CSP%29+formulations+for+FPGA+system+design%22