VLSI Implementation Of A Systolic Array Viterbi Decoder
This project is on developing a Vi terbi decoder which uses the trace-back method structured in a systolic array fashion. It is believed that this architecture can reduce the size of the decoder as it minimizes the connections between component modules and requires a smaller storage space. The trace...
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| Format: | Thesis |
| Language: | en |
| Published: |
1995
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| Online Access: | http://eprints.usm.my/63228/1/Pages%20from%20Norlaili%20binti%20Mohd.%20Noh.pdf http://eprints.usm.my/63228/ |
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| _version_ | 1850174658252374016 |
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| author | Mohd. Noh, Norlaili |
| author_facet | Mohd. Noh, Norlaili |
| author_sort | Mohd. Noh, Norlaili |
| building | Hamzah Sendut Library |
| collection | Institutional Repository |
| content_provider | Universiti Sains Malaysia |
| content_source | USM Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | This project is on developing a Vi terbi decoder which uses the trace-back method structured in a systolic array fashion. It is believed that this architecture can reduce the size of the decoder as it minimizes the connections between component modules and requires a smaller storage space. The trace-back method can reduce the amount of
hardware which is normally a problem with register exchange decoder. It is also suitable for achieving a higher speed of operation as tracking, updating and storage of the
information sequence can be accomplished simultaneously during a single clock cycle. |
| format | Thesis |
| id | my.usm.eprints.63228 |
| institution | Universiti Sains Malaysia |
| language | en |
| publishDate | 1995 |
| record_format | eprints |
| spelling | my.usm.eprints.63228 http://eprints.usm.my/63228/ VLSI Implementation Of A Systolic Array Viterbi Decoder Mohd. Noh, Norlaili LC5800-5808 Distance education. This project is on developing a Vi terbi decoder which uses the trace-back method structured in a systolic array fashion. It is believed that this architecture can reduce the size of the decoder as it minimizes the connections between component modules and requires a smaller storage space. The trace-back method can reduce the amount of hardware which is normally a problem with register exchange decoder. It is also suitable for achieving a higher speed of operation as tracking, updating and storage of the information sequence can be accomplished simultaneously during a single clock cycle. 1995-03 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/63228/1/Pages%20from%20Norlaili%20binti%20Mohd.%20Noh.pdf Mohd. Noh, Norlaili (1995) VLSI Implementation Of A Systolic Array Viterbi Decoder. Masters thesis, Universiti Sains Malaysia. |
| spellingShingle | LC5800-5808 Distance education. Mohd. Noh, Norlaili VLSI Implementation Of A Systolic Array Viterbi Decoder |
| title | VLSI Implementation Of A Systolic Array Viterbi Decoder |
| title_full | VLSI Implementation Of A Systolic Array Viterbi Decoder |
| title_fullStr | VLSI Implementation Of A Systolic Array Viterbi Decoder |
| title_full_unstemmed | VLSI Implementation Of A Systolic Array Viterbi Decoder |
| title_short | VLSI Implementation Of A Systolic Array Viterbi Decoder |
| title_sort | vlsi implementation of a systolic array viterbi decoder |
| topic | LC5800-5808 Distance education. |
| url | http://eprints.usm.my/63228/1/Pages%20from%20Norlaili%20binti%20Mohd.%20Noh.pdf http://eprints.usm.my/63228/ |
| url_provider | http://eprints.usm.my/ |