VLSI Implementation Of A Systolic Array Viterbi Decoder
This project is on developing a Vi terbi decoder which uses the trace-back method structured in a systolic array fashion. It is believed that this architecture can reduce the size of the decoder as it minimizes the connections between component modules and requires a smaller storage space. The trace...
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| Format: | Thesis |
| Language: | en |
| Published: |
1995
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| Online Access: | http://eprints.usm.my/63228/1/Pages%20from%20Norlaili%20binti%20Mohd.%20Noh.pdf http://eprints.usm.my/63228/ |
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