Low Power Multiplier Accumulator (MAC) unit using Sleepy Stack technique

The main objective of this project is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, the focus is on leakage power reduction. In this project, a novel circuit structure called “sleepy stack” is presented. The sleepy stack is a combination of two w...

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Bibliographic Details

Main Author:	Aaron Selvam Thangamany
Other Authors:	Nazuhusna Khalid (Advisor)
Format:	Learning Object
Language:	en
Published:	Universiti Malaysia Perlis 2008
Subjects:	Multipliers Multipliers (Mathematical analysis) Very Large Scale Integration (VLSI) Transistors Sleepy Stack technique Metal oxide semiconductors, Complementary Multiplier accumulator (MAC)
Online Access:	http://dspace.unimap.edu.my/123456789/1951
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