Optimization of gate dielectric thickness in PMOS structure using silvaco TCD tools
The dielectric layer in Metal Oxide Semiconductor Field Effect transistor (MOSFET) is a layer of very thin oxide which serves as insulator between the gate and channel. It’s also known as gate oxide or gate dielectric. This paper presents the effects of gate oxide thickness on p-channel MOSFET (PMOS...
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| Format: | Student Project |
| Language: | en |
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2008
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| Online Access: | https://ir.uitm.edu.my/id/eprint/123003/1/123003.pdf https://ir.uitm.edu.my/id/eprint/123003/ |
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| _version_ | 1847097741616873472 |
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| author | Bakri, Ayub |
| author_facet | Bakri, Ayub |
| author_sort | Bakri, Ayub |
| building | Tun Abdul Razak Library |
| collection | Institutional Repository |
| content_provider | Universiti Teknologi Mara |
| content_source | UiTM Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | The dielectric layer in Metal Oxide Semiconductor Field Effect transistor (MOSFET) is a layer of very thin oxide which serves as insulator between the gate and channel. It’s also known as gate oxide or gate dielectric. This paper presents the effects of gate oxide thickness on p-channel MOSFET (PMOS) performance by optimizing the gate oxide thickness using Silvaco Technology Computer Aided Design (TCAD) software. The gate oxide thickness was found directly proportional to the threshold voltage. By using Silvaco TCAD, the optimum value obtained for gate oxide thickness is 3 nm. In the oxidation process the oxidation time is the best optimizer parameter compared to pressure and temperature. The optimum amount of HCl in oxidation process is 3%. |
| format | Student Project |
| id | my.uitm.ir-123003 |
| institution | Universiti Teknologi Mara |
| language | en |
| publishDate | 2008 |
| record_format | eprints |
| spelling | my.uitm.ir-1230032025-10-14T02:26:59Z https://ir.uitm.edu.my/id/eprint/123003/ Optimization of gate dielectric thickness in PMOS structure using silvaco TCD tools Bakri, Ayub Apparatus and materials Dielectric devices The dielectric layer in Metal Oxide Semiconductor Field Effect transistor (MOSFET) is a layer of very thin oxide which serves as insulator between the gate and channel. It’s also known as gate oxide or gate dielectric. This paper presents the effects of gate oxide thickness on p-channel MOSFET (PMOS) performance by optimizing the gate oxide thickness using Silvaco Technology Computer Aided Design (TCAD) software. The gate oxide thickness was found directly proportional to the threshold voltage. By using Silvaco TCAD, the optimum value obtained for gate oxide thickness is 3 nm. In the oxidation process the oxidation time is the best optimizer parameter compared to pressure and temperature. The optimum amount of HCl in oxidation process is 3%. 2008 Student Project NonPeerReviewed text en https://ir.uitm.edu.my/id/eprint/123003/1/123003.pdf Bakri, Ayub (2008) Optimization of gate dielectric thickness in PMOS structure using silvaco TCD tools. (2008) [Student Project] <http://terminalib.uitm.edu.my/123003.pdf> (Unpublished) |
| spellingShingle | Apparatus and materials Dielectric devices Bakri, Ayub Optimization of gate dielectric thickness in PMOS structure using silvaco TCD tools |
| title | Optimization of gate dielectric thickness in PMOS structure using silvaco TCD tools |
| title_full | Optimization of gate dielectric thickness in PMOS structure using silvaco TCD tools |
| title_fullStr | Optimization of gate dielectric thickness in PMOS structure using silvaco TCD tools |
| title_full_unstemmed | Optimization of gate dielectric thickness in PMOS structure using silvaco TCD tools |
| title_short | Optimization of gate dielectric thickness in PMOS structure using silvaco TCD tools |
| title_sort | optimization of gate dielectric thickness in pmos structure using silvaco tcd tools |
| topic | Apparatus and materials Dielectric devices |
| url | https://ir.uitm.edu.my/id/eprint/123003/1/123003.pdf https://ir.uitm.edu.my/id/eprint/123003/ |
| url_provider | http://ir.uitm.edu.my/ |