Low power sample and hold circuit for pipelined ADC using 0.18µm CMOS technology / Nurhakimah Abd Aziz
This paper discusses the design and analysis of the improved sample-and-hold circuit as a front-end block of low power and high gain pipelined analog to digital converter (ADC). This research will use switch-capacitor sample and hold circuit (SHC) which is exploiting multistage amplifier to minimize...
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| Format: | Thesis |
| Language: | en |
| Published: |
2012
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| Online Access: | https://ir.uitm.edu.my/id/eprint/114378/1/114378.pdf https://ir.uitm.edu.my/id/eprint/114378/ |
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