Designing clock generator and BCD counter for a frequency counter using VHDL / Mohd Firdaus Ahmad
This paper presents a development of a frequency counter using VHDL under Xilinx environment. This frequency counter is based on the premise of counting the incoming known frequency's rising edge for digital signal as a predetermined fixed amount of time, or GATE. The circuit is partitioned in...
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| Format: | Thesis |
| Language: | en |
| Published: |
2005
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| Subjects: | |
| Online Access: | https://ir.uitm.edu.my/id/eprint/102741/1/102741.pdf https://ir.uitm.edu.my/id/eprint/102741/ |
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| Summary: | This paper presents a development of a frequency counter using VHDL under Xilinx environment. This frequency counter is based on the premise of counting the incoming known frequency's rising edge for digital signal as a predetermined fixed amount of time, or GATE. The circuit is partitioned in two sequences individual circuit namely as Clock Generator and BCD Counter. The sub circuits for clock generator are Oscillator 4 (OSC4) and counters according to the chosen frequency generated. The circuit for BCD Counter is a main circuit. There are three types of modelling used as an existing method such as behavioural, structural and data flow. Other modelling technique that is also considered is the state machine as an additional method which is coded using VHDL where the results are observable in form of timing diagrams. |
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