Automatic Generation of Test Instructions for Structural Faults in Processor Cores using Satisfiability
Instruction execution from the cache to detect the faulty chips in native mode has proven its effectiveness with high performance and low power consumption. Gate-level ATPG are time expensive and difficult to implement for large design. In this paper, we proposed an RTL-based methodology framework t...
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| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2013
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| Online Access: | http://eprints.utp.edu.my/11973/1/ISOCC2013.pdf http://eprints.utp.edu.my/11973/ |
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