Power efficient blockchain miner accelerator design
Blockchain related technology nowadays involves cryptocurrency, supply chains, global trades, land registration, and logistics. While blockchain's unique characteristics provides benefits such as increase transparency, integrity and security of data that is shared across the network, employing...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2022
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/99518/1/LimCalvinMSKE2022.pdf http://eprints.utm.my/id/eprint/99518/ http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:149941 |
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| Summary: | Blockchain related technology nowadays involves cryptocurrency, supply chains, global trades, land registration, and logistics. While blockchain's unique characteristics provides benefits such as increase transparency, integrity and security of data that is shared across the network, employing blockchain requires very high energy consumption due to its mining process. Mining process’s high energy consumption was due to the Proof of work (PoW) consensus protocols on the blockchain network which utilizing the double SHA-256 algorithm to compute the hash of the block header. This ensures that each block of database entry that is distributed on the network is confirmed and encrypted, increasing integrity and data security. Most of the researches and improvement are focus on throughput and performance on the hardware as a standalone accelerator, overlooking the importance of power efficiency which is also one of the main factors in current industry system-on-a-chip (SoC) design. The data dependency among loops in the double SHA-256 algorithm was one of the main aspects which leads to high energy consumption due to the extensive calculation process for multiple loops. This paper proposing a power efficient blockchain miner accelerator design to optimize the power consumption of the blockchain miner accelerator from the design perspective which relates to clock gating, high voltage and low voltage threshold (HVT & LVT) standard cell technology library. There are 3 main intensions, first is to implement a SHA-256 baseline architecture in ASIC with Synopsys Verilog Compiler and Simulator (VCS) for circuit design verification and Design compiler (DC) for circuit synthesis using SAED 32nm standard cell library as the PDK (Process Design Kit). Next is to design a double SHA-256 accelerator using the same tools and technology and compare the two algorithms in terms of power consumption. Last is to analyse the power consumption of double SHA-256 accelerator with the implementation of clock gating optimization and different voltage threshold cell (HVT & LVT) setup. Results from the research shows that HVT synthesized circuit design with clock gating implementation for the accelerator produced good power efficiency. |
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