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Comprehensive analysis of gate oxide short in junctionless fin field effect transistor

Junctionless (JL) FinFET is one of the most promising alternatives to FinFET and planar MOSFET for future performance enhancements. The complexity of the JL FinFET manufacturing process has prompted difficulties in reliable device testing. Gate oxide short (GOS) is one of the most common faults that...

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Main Authors: Rahman, Md. Wahidur, Alias, N. Ezaila, Hamzah, Afiq, Tan, M. L. Peng, Kamisian, Izam
Format: Conference or Workshop Item
Published: 2022
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/98866/
http://dx.doi.org/10.1109/ICSE56004.2022.9863184
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spelling my.utm.988662023-02-02T09:55:58Z http://eprints.utm.my/id/eprint/98866/ Comprehensive analysis of gate oxide short in junctionless fin field effect transistor Rahman, Md. Wahidur Alias, N. Ezaila Hamzah, Afiq Tan, M. L. Peng Kamisian, Izam TK Electrical engineering. Electronics Nuclear engineering Junctionless (JL) FinFET is one of the most promising alternatives to FinFET and planar MOSFET for future performance enhancements. The complexity of the JL FinFET manufacturing process has prompted difficulties in reliable device testing. Gate oxide short (GOS) is one of the most common faults that substantially influence circuit reliability, specifically in FinFET device structure. In this work, GOS defect model is presented for both n-channel and p-channel JL FinFET and JL FinFET-based inverter by introducing the defect as a pinhole designated by small cuboid cuts of different sizes for several coordination in the dielectric and filled with gate material. The electrical characteristics of 15nm n- and p-channel JL FinFET with fin height and width of 10nm, source/drain, channel and substrate doping concentration of 1.5×1019 cm-3, and work function of 4.76eV and 4.52eV for n- and p-channel are successfully simulated by using Synopsys Sentaurus TCAD Tools where Vth, SS, and DIBL are 0.371V, 75.7mV/dec and 42.7mV for n-channel and 0.3298V, 79.1mV/dec and 48.9mV for p-channel JL FinFET respectively that is compared with post GOS defect injection. The high-to-low delay time (tHL) is 1.61ps and low-to-high delay time (tLH) is 1.74ps for the defect-free inverter that is compared to the defected one where the tHL is 16.1 % and tLH is 22.4 % smaller than defective inverter. The findings of this research potentially result in the formation of a realistic analytical GOS fault model for circuit-level modeling. 2022 Conference or Workshop Item PeerReviewed Rahman, Md. Wahidur and Alias, N. Ezaila and Hamzah, Afiq and Tan, M. L. Peng and Kamisian, Izam (2022) Comprehensive analysis of gate oxide short in junctionless fin field effect transistor. In: 2022 IEEE International Conference on Semiconductor Electronics, ICSE 2022, 15 - 17 August 2022, Virtual, Kuala Lumpur. http://dx.doi.org/10.1109/ICSE56004.2022.9863184
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Rahman, Md. Wahidur
Alias, N. Ezaila
Hamzah, Afiq
Tan, M. L. Peng
Kamisian, Izam
Comprehensive analysis of gate oxide short in junctionless fin field effect transistor
description Junctionless (JL) FinFET is one of the most promising alternatives to FinFET and planar MOSFET for future performance enhancements. The complexity of the JL FinFET manufacturing process has prompted difficulties in reliable device testing. Gate oxide short (GOS) is one of the most common faults that substantially influence circuit reliability, specifically in FinFET device structure. In this work, GOS defect model is presented for both n-channel and p-channel JL FinFET and JL FinFET-based inverter by introducing the defect as a pinhole designated by small cuboid cuts of different sizes for several coordination in the dielectric and filled with gate material. The electrical characteristics of 15nm n- and p-channel JL FinFET with fin height and width of 10nm, source/drain, channel and substrate doping concentration of 1.5×1019 cm-3, and work function of 4.76eV and 4.52eV for n- and p-channel are successfully simulated by using Synopsys Sentaurus TCAD Tools where Vth, SS, and DIBL are 0.371V, 75.7mV/dec and 42.7mV for n-channel and 0.3298V, 79.1mV/dec and 48.9mV for p-channel JL FinFET respectively that is compared with post GOS defect injection. The high-to-low delay time (tHL) is 1.61ps and low-to-high delay time (tLH) is 1.74ps for the defect-free inverter that is compared to the defected one where the tHL is 16.1 % and tLH is 22.4 % smaller than defective inverter. The findings of this research potentially result in the formation of a realistic analytical GOS fault model for circuit-level modeling.
format Conference or Workshop Item
author Rahman, Md. Wahidur
Alias, N. Ezaila
Hamzah, Afiq
Tan, M. L. Peng
Kamisian, Izam
author_facet Rahman, Md. Wahidur
Alias, N. Ezaila
Hamzah, Afiq
Tan, M. L. Peng
Kamisian, Izam
author_sort Rahman, Md. Wahidur
title Comprehensive analysis of gate oxide short in junctionless fin field effect transistor
title_short Comprehensive analysis of gate oxide short in junctionless fin field effect transistor
title_full Comprehensive analysis of gate oxide short in junctionless fin field effect transistor
title_fullStr Comprehensive analysis of gate oxide short in junctionless fin field effect transistor
title_full_unstemmed Comprehensive analysis of gate oxide short in junctionless fin field effect transistor
title_sort comprehensive analysis of gate oxide short in junctionless fin field effect transistor
publishDate 2022
url http://eprints.utm.my/id/eprint/98866/
http://dx.doi.org/10.1109/ICSE56004.2022.9863184
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score 13.211869

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