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Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET

The digital multipliers are the assertive sources of power exhaustion in the modern digital systems. To perform most efficient arithmetic based calculations, Montgomery multiplication can be one of the best alternatives for other conventional methods in digital architecture as high-speed multipliers...

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Main Authors:	Mathangi, R., Alias, N. E., Hamzah, A., Tan, M. L. P., Mathan, N.
Format:	Conference or Workshop Item
Language:	English
Published:	2021
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/96082/1/RMathangi2021_PerformanceAnalysisofanEfficientMontgomery.pdf http://eprints.utm.my/id/eprint/96082/ http://dx.doi.org/10.1109/ICECCE52056.2021.9514146
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spelling	my.utm.960822022-07-03T07:45:54Z http://eprints.utm.my/id/eprint/96082/ Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET Mathangi, R. Alias, N. E. Hamzah, A. Tan, M. L. P. Mathan, N. TK Electrical engineering. Electronics Nuclear engineering The digital multipliers are the assertive sources of power exhaustion in the modern digital systems. To perform most efficient arithmetic based calculations, Montgomery multiplication can be one of the best alternatives for other conventional methods in digital architecture as high-speed multipliers are desired for its remarkable performance. The main drawback of the digital multipliers is that power exhaustion is very high when compared to the other elements of the digital circuit. Shift register is the one of the most important component in a digital multiplier which consumes comparatively higher power than the other components. Shift registers contains a series of D-flip flops to store the digital data. In order to obtain a notable improvement in terms of power consumption at the chip level, the flip-flop can be modified to achieve the reduction of average power in the multiplier. The Fin-Field Effect Transistor (FinFET) is a promising candidate to overcome fundamental limitations of its Silicon based alternative MOSFET. However, there seems to be an increase in leakage power and delay. The Junctionless FinFET with uniform doping in the channel proves to offer a better performance in terms of overall speed, power consumption and power delay product. The architecture has been designed in 7nm FinFET and JL-FinFET in Synopsys HSpice and Silvaco TCAD. The results of the Montgomery Multiplier affirms that the overall energy is improved by 55% and speed of the device by 35% as compared to the existing Montgomery Multiplier. 2021 Conference or Workshop Item PeerReviewed application/pdf en http://eprints.utm.my/id/eprint/96082/1/RMathangi2021_PerformanceAnalysisofanEfficientMontgomery.pdf Mathangi, R. and Alias, N. E. and Hamzah, A. and Tan, M. L. P. and Mathan, N. (2021) Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET. In: 3rd International Conference on Electrical, Communication and Computer Engineering, ICECCE 2021, 12 June 2021 - 13 June 2021, Kuala Lumpur, Malaysia. http://dx.doi.org/10.1109/ICECCE52056.2021.9514146
institution	Universiti Teknologi Malaysia
building	UTM Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Teknologi Malaysia
content_source	UTM Institutional Repository
url_provider	http://eprints.utm.my/
language	English
topic	TK Electrical engineering. Electronics Nuclear engineering
spellingShingle	TK Electrical engineering. Electronics Nuclear engineering Mathangi, R. Alias, N. E. Hamzah, A. Tan, M. L. P. Mathan, N. Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET
description	The digital multipliers are the assertive sources of power exhaustion in the modern digital systems. To perform most efficient arithmetic based calculations, Montgomery multiplication can be one of the best alternatives for other conventional methods in digital architecture as high-speed multipliers are desired for its remarkable performance. The main drawback of the digital multipliers is that power exhaustion is very high when compared to the other elements of the digital circuit. Shift register is the one of the most important component in a digital multiplier which consumes comparatively higher power than the other components. Shift registers contains a series of D-flip flops to store the digital data. In order to obtain a notable improvement in terms of power consumption at the chip level, the flip-flop can be modified to achieve the reduction of average power in the multiplier. The Fin-Field Effect Transistor (FinFET) is a promising candidate to overcome fundamental limitations of its Silicon based alternative MOSFET. However, there seems to be an increase in leakage power and delay. The Junctionless FinFET with uniform doping in the channel proves to offer a better performance in terms of overall speed, power consumption and power delay product. The architecture has been designed in 7nm FinFET and JL-FinFET in Synopsys HSpice and Silvaco TCAD. The results of the Montgomery Multiplier affirms that the overall energy is improved by 55% and speed of the device by 35% as compared to the existing Montgomery Multiplier.
format	Conference or Workshop Item
author	Mathangi, R. Alias, N. E. Hamzah, A. Tan, M. L. P. Mathan, N.
author_facet	Mathangi, R. Alias, N. E. Hamzah, A. Tan, M. L. P. Mathan, N.
author_sort	Mathangi, R.
title	Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET
title_short	Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET
title_full	Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET
title_fullStr	Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET
title_full_unstemmed	Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET
title_sort	performance analysis of an efficient montgomery multiplier using 7nm finfet and junctionless finfet
publishDate	2021
url	http://eprints.utm.my/id/eprint/96082/1/RMathangi2021_PerformanceAnalysisofanEfficientMontgomery.pdf http://eprints.utm.my/id/eprint/96082/ http://dx.doi.org/10.1109/ICECCE52056.2021.9514146
_version_	1738510321224515584
score	13.211869

Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET

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