Design of a lan interfacing module for a softcore processor AMIR CPU
An AMIR CPU is a novel 32-bit softcore processor developed from the improvement of the weakness of existing Intel x86 and ARM architectures which has its own local I/O memory and easier ISA (Instruction Set Architecture) compared to RISC (Reduced Instruction Set Computer) and CISC (Complex Instructi...
Saved in:
Main Author: | Lim, Hui Teng |
---|---|
Format: | Thesis |
Language: | English |
Published: |
2020
|
Subjects: | |
Online Access: | http://eprints.utm.my/id/eprint/93021/1/LimHuiTengMSKE2020.pdf http://eprints.utm.my/id/eprint/93021/ http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:135859 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
FPGA-based design of a math co-processor for the Amir CPU
by: Tan, Arthur Foo Yen
Published: (2020) -
Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors
by: Akhtar, Mohammad Nishat
Published: (2013) -
GCC toolchain's c compiler wrapper for the Amir CPU assembly language
by: Ee, Eline Bee Ling
Published: (2020) -
Application Specific Instruction Set Processor (ASIP) Design In An 8-Bit Softcore Microcontroller
by: Salim, Sani Irwan, et al.
Published: (2018) -
Wired LAN Door Access Controller With Web-based Interface
by: Ong , Wen Sher
Published: (2010)