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Register transfer level design of transpose memory for the two-dimension inverse discrete cosine transform for high efficiency video coding

The rapid revolution in consumer devices have caused in a variety of emerging video coding applications which contribute the aggressive demands on video compression requirement. The requirement of video compression efficiency getting higher. Today, Advance Video Coding (AVC) standard was replaced by...

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Main Author: Goh, Dih Jiann
Format: Thesis
Language:English
Published: 2018
Subjects:
QA75 Electronic computers. Computer science
Online Access:http://eprints.utm.my/id/eprint/79301/1/Goh%20Dih%20JiannMFC2018.pdf
http://eprints.utm.my/id/eprint/79301/
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spelling my.utm.793012018-10-14T08:42:09Z http://eprints.utm.my/id/eprint/79301/ Register transfer level design of transpose memory for the two-dimension inverse discrete cosine transform for high efficiency video coding Goh, Dih Jiann QA75 Electronic computers. Computer science The rapid revolution in consumer devices have caused in a variety of emerging video coding applications which contribute the aggressive demands on video compression requirement. The requirement of video compression efficiency getting higher. Today, Advance Video Coding (AVC) standard was replaced by the new High Efficiency Video Coding (HEVC) video compression standard due to major advance in compression compare to former. However, optimizing coding efficiency in HEVC is the root of increased computational complexity. Thus, Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) are absolute necessary accelerator in HEVC hardware implementation. However, the hardware design of these accelerator complexity become more complicated due to flexibility given by the new video compression standard. This project aimed to design Two-Dimension Inverse Discrete Cosine Transform (2D IDCT) hardware transpose memory using hardware description language. The first objective in this project was implemented transpose memory that support different transform block dimension (4x4, 8x8, 16x16 and 32x32 transform unit). Both register-based design and RAM-based design were implemented. Secondly, a test bench was designed to validate the functionality of RTL design. Third, the integration was done between 1D IDCT building block with designed transpose memory and overall system functionality was validated. Finally, analysis was done to find out trade-off in performance, resource and power between register-based and dedicate RAM based transpose memory. The results show that register-based 2D IDCT have 2.24 times better throughput and 35.6% less energy consumption compare to RAM-based 2D IDCT. However, register-based 2D IDCT have 30 times more resource utilization compare to RAM-based 2-D IDCT. Thus, RAM-based 2D IDCT is more suitable for small electronic device. If area expenses is negligible and performance is needed, register-based 2D IDCT can be considered. 2018 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/id/eprint/79301/1/Goh%20Dih%20JiannMFC2018.pdf Goh, Dih Jiann (2018) Register transfer level design of transpose memory for the two-dimension inverse discrete cosine transform for high efficiency video coding. Masters thesis, Universiti Teknologi Malaysia, Faculty of Computing.
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic QA75 Electronic computers. Computer science
spellingShingle QA75 Electronic computers. Computer science
Goh, Dih Jiann
Register transfer level design of transpose memory for the two-dimension inverse discrete cosine transform for high efficiency video coding
description The rapid revolution in consumer devices have caused in a variety of emerging video coding applications which contribute the aggressive demands on video compression requirement. The requirement of video compression efficiency getting higher. Today, Advance Video Coding (AVC) standard was replaced by the new High Efficiency Video Coding (HEVC) video compression standard due to major advance in compression compare to former. However, optimizing coding efficiency in HEVC is the root of increased computational complexity. Thus, Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) are absolute necessary accelerator in HEVC hardware implementation. However, the hardware design of these accelerator complexity become more complicated due to flexibility given by the new video compression standard. This project aimed to design Two-Dimension Inverse Discrete Cosine Transform (2D IDCT) hardware transpose memory using hardware description language. The first objective in this project was implemented transpose memory that support different transform block dimension (4x4, 8x8, 16x16 and 32x32 transform unit). Both register-based design and RAM-based design were implemented. Secondly, a test bench was designed to validate the functionality of RTL design. Third, the integration was done between 1D IDCT building block with designed transpose memory and overall system functionality was validated. Finally, analysis was done to find out trade-off in performance, resource and power between register-based and dedicate RAM based transpose memory. The results show that register-based 2D IDCT have 2.24 times better throughput and 35.6% less energy consumption compare to RAM-based 2D IDCT. However, register-based 2D IDCT have 30 times more resource utilization compare to RAM-based 2-D IDCT. Thus, RAM-based 2D IDCT is more suitable for small electronic device. If area expenses is negligible and performance is needed, register-based 2D IDCT can be considered.
format Thesis
author Goh, Dih Jiann
author_facet Goh, Dih Jiann
author_sort Goh, Dih Jiann
title Register transfer level design of transpose memory for the two-dimension inverse discrete cosine transform for high efficiency video coding
title_short Register transfer level design of transpose memory for the two-dimension inverse discrete cosine transform for high efficiency video coding
title_full Register transfer level design of transpose memory for the two-dimension inverse discrete cosine transform for high efficiency video coding
title_fullStr Register transfer level design of transpose memory for the two-dimension inverse discrete cosine transform for high efficiency video coding
title_full_unstemmed Register transfer level design of transpose memory for the two-dimension inverse discrete cosine transform for high efficiency video coding
title_sort register transfer level design of transpose memory for the two-dimension inverse discrete cosine transform for high efficiency video coding
publishDate 2018
url http://eprints.utm.my/id/eprint/79301/1/Goh%20Dih%20JiannMFC2018.pdf
http://eprints.utm.my/id/eprint/79301/
_version_ 1643658155906826240
score 13.211869

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