Cover Image

RTL implementation of one-sided jacobi algorithm for singular value decomposition

Multi-dimensional digital signal processing such as image processing and image reconstruction involve manipulating of matrix data. Better quality images involve large amount of data, which result in unacceptably slow computation. A parallel processing scheme is a possible solution to solve this prob...

Full description

Saved in:
Bibliographic Details
Main Author: Wan Mohamad, Wan Ahmad Zainie
Format: Thesis
Language:English
Published: 2016
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/78060/1/WanAhmadZainieMFKE20161.pdf
http://eprints.utm.my/id/eprint/78060/
http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:90252
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.utm.78060
record_format eprints
spelling my.utm.780602018-07-23T05:33:24Z http://eprints.utm.my/id/eprint/78060/ RTL implementation of one-sided jacobi algorithm for singular value decomposition Wan Mohamad, Wan Ahmad Zainie TK Electrical engineering. Electronics Nuclear engineering Multi-dimensional digital signal processing such as image processing and image reconstruction involve manipulating of matrix data. Better quality images involve large amount of data, which result in unacceptably slow computation. A parallel processing scheme is a possible solution to solve this problem. This project presented an analysis and comparison to various algorithms for widely used matrix decomposition techniques and various computer architectures. As the result, a parallel implementation of one-sided Jacobi algorithm for computing singular value decomposition (SVD) of a 2х2 matrix on field programmable gate arrays (FPGA) is developed. The proposed SVD design is based on pipelined-datapath architecture The design process is started by evaluating the algorithm using Matlab, design datapath unit and control unit, coding in SystemVerilog HDL, verification and synthesis using Quartus II and simulated on ModelSim-Altera. The original matrix size of 4x4 and 8x8 is used to with the SVD processing element (PE). The result are compared with the Matlab version of the algorithm to evaluate the PE. The computation of SVD can be speed-up of more than 2 by increasing the number of PE at the cost of increased in circuit area. 2016-06 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/id/eprint/78060/1/WanAhmadZainieMFKE20161.pdf Wan Mohamad, Wan Ahmad Zainie (2016) RTL implementation of one-sided jacobi algorithm for singular value decomposition. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering. http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:90252
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Wan Mohamad, Wan Ahmad Zainie
RTL implementation of one-sided jacobi algorithm for singular value decomposition
description Multi-dimensional digital signal processing such as image processing and image reconstruction involve manipulating of matrix data. Better quality images involve large amount of data, which result in unacceptably slow computation. A parallel processing scheme is a possible solution to solve this problem. This project presented an analysis and comparison to various algorithms for widely used matrix decomposition techniques and various computer architectures. As the result, a parallel implementation of one-sided Jacobi algorithm for computing singular value decomposition (SVD) of a 2х2 matrix on field programmable gate arrays (FPGA) is developed. The proposed SVD design is based on pipelined-datapath architecture The design process is started by evaluating the algorithm using Matlab, design datapath unit and control unit, coding in SystemVerilog HDL, verification and synthesis using Quartus II and simulated on ModelSim-Altera. The original matrix size of 4x4 and 8x8 is used to with the SVD processing element (PE). The result are compared with the Matlab version of the algorithm to evaluate the PE. The computation of SVD can be speed-up of more than 2 by increasing the number of PE at the cost of increased in circuit area.
format Thesis
author Wan Mohamad, Wan Ahmad Zainie
author_facet Wan Mohamad, Wan Ahmad Zainie
author_sort Wan Mohamad, Wan Ahmad Zainie
title RTL implementation of one-sided jacobi algorithm for singular value decomposition
title_short RTL implementation of one-sided jacobi algorithm for singular value decomposition
title_full RTL implementation of one-sided jacobi algorithm for singular value decomposition
title_fullStr RTL implementation of one-sided jacobi algorithm for singular value decomposition
title_full_unstemmed RTL implementation of one-sided jacobi algorithm for singular value decomposition
title_sort rtl implementation of one-sided jacobi algorithm for singular value decomposition
publishDate 2016
url http://eprints.utm.my/id/eprint/78060/1/WanAhmadZainieMFKE20161.pdf
http://eprints.utm.my/id/eprint/78060/
http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:90252
_version_ 1643657715913850880
score 13.211869

Similar Items