Test register insertion at RTL based on reduced BIST
Built-in self-test (BIST) method has high area overhead and long test application time. In this paper, a new BIST method is proposed at register transfer level (RTL) as a design for testability (DFT) method to modify a given RTL circuit to a reduced BISTable RTL circuit. First, we introduce modellin...
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2017
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my.utm.767342018-04-30T13:56:06Z http://eprints.utm.my/id/eprint/76734/ Test register insertion at RTL based on reduced BIST Paraman, N. Ooi, C. Y. Sha'ameri, A. Z. Fujiwara, H. TK Electrical engineering. Electronics Nuclear engineering Built-in self-test (BIST) method has high area overhead and long test application time. In this paper, a new BIST method is proposed at register transfer level (RTL) as a design for testability (DFT) method to modify a given RTL circuit to a reduced BISTable RTL circuit. First, we introduce modelling method called extended R-graph to represent the register connectivity of an RTL circuit. The original register in the RTL circuit is modified into multiple input signature registers (MISRs) as test register. The selection of MISR is performed by extended minimum feedback vertex set (MFVS) algorithm that identifies a set of vertices (representing test register) which breaks all the loops of extended R-graph with minimal cost when vertices are removed. It has been proven through simulation that the proposed BIST method has lower area overhead of 32.9% on average and achieves comparably high fault coverage compared to the previous method, concurrent BIST using ITC'99 benchmark circuits. Penerbit UTM Press 2017 Article PeerReviewed Paraman, N. and Ooi, C. Y. and Sha'ameri, A. Z. and Fujiwara, H. (2017) Test register insertion at RTL based on reduced BIST. Jurnal Teknologi, 79 (1). pp. 81-88. ISSN 0127-9696 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85008217112&doi=10.11113%2fjt.v79.8479&partnerID=40&md5=2f973c045c17e3ab5bb5e3694723fd20 DOI:10.11113/jt.v79.8479 |
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TK Electrical engineering. Electronics Nuclear engineering Paraman, N. Ooi, C. Y. Sha'ameri, A. Z. Fujiwara, H. Test register insertion at RTL based on reduced BIST |
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Built-in self-test (BIST) method has high area overhead and long test application time. In this paper, a new BIST method is proposed at register transfer level (RTL) as a design for testability (DFT) method to modify a given RTL circuit to a reduced BISTable RTL circuit. First, we introduce modelling method called extended R-graph to represent the register connectivity of an RTL circuit. The original register in the RTL circuit is modified into multiple input signature registers (MISRs) as test register. The selection of MISR is performed by extended minimum feedback vertex set (MFVS) algorithm that identifies a set of vertices (representing test register) which breaks all the loops of extended R-graph with minimal cost when vertices are removed. It has been proven through simulation that the proposed BIST method has lower area overhead of 32.9% on average and achieves comparably high fault coverage compared to the previous method, concurrent BIST using ITC'99 benchmark circuits. |
| format |
Article |
| author |
Paraman, N. Ooi, C. Y. Sha'ameri, A. Z. Fujiwara, H. |
| author_facet |
Paraman, N. Ooi, C. Y. Sha'ameri, A. Z. Fujiwara, H. |
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Paraman, N. |
| title |
Test register insertion at RTL based on reduced BIST |
| title_short |
Test register insertion at RTL based on reduced BIST |
| title_full |
Test register insertion at RTL based on reduced BIST |
| title_fullStr |
Test register insertion at RTL based on reduced BIST |
| title_full_unstemmed |
Test register insertion at RTL based on reduced BIST |
| title_sort |
test register insertion at rtl based on reduced bist |
| publisher |
Penerbit UTM Press |
| publishDate |
2017 |
| url |
http://eprints.utm.my/id/eprint/76734/ https://www.scopus.com/inward/record.uri?eid=2-s2.0-85008217112&doi=10.11113%2fjt.v79.8479&partnerID=40&md5=2f973c045c17e3ab5bb5e3694723fd20 |
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13.211869 |