SVA checker generator for FPGA-based verification platform
This paper discusses development of FPGA-based verification platform which consists of System' Verilog assertion (SVA) checker generator to synthesize SVA into Verilog code. We derive a lookup table that consists of SVA operators and their corresponding synthesizable RTL coding. Assertion check...
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| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Published: |
Institute of Electrical and Electronics Engineers Inc.
2016
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/73107/ https://www.scopus.com/inward/record.uri?eid=2-s2.0-84983454978&doi=10.1109%2fISCAS.2016.7538906&partnerID=40&md5=43d58ebd2bdf919b41e242ce9a460a05 |
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