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Performance evaluation of 14nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis

As the technology node size decreases, the number of static random-access memory (SRAM) cells on a single word line increases. The coupling capacitance will increase with the increase of the load of word line, which reduces the performance of SRAM, more obvious in the SRAM signal delay and the SRAM...

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Main Authors: Lim, Wei, Chin, Huei Chaeng, Lim, Cheng Siong, Tan, Michael Loong Peng
Format: Article
Language:English
Published: Hindawi Publishing Corporation 2014
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/54446/1/WeiLim2014_Performanceevaluationof14nm.pdf
http://eprints.utm.my/id/eprint/54446/
http://dx.doi.org/10.1155/2014/820763
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spelling my.utm.544462018-08-12T03:55:58Z http://eprints.utm.my/id/eprint/54446/ Performance evaluation of 14nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis Lim, Wei Chin, Huei Chaeng Lim, Cheng Siong Tan, Michael Loong Peng TK Electrical engineering. Electronics Nuclear engineering As the technology node size decreases, the number of static random-access memory (SRAM) cells on a single word line increases. The coupling capacitance will increase with the increase of the load of word line, which reduces the performance of SRAM, more obvious in the SRAM signal delay and the SRAM power usage. The main purpose of this study is to investigate the stability and evaluate the power consumption of a 14 nm gate length FinFET-based 6T SRAM cell functionality for direct current (DC) and transient circuit analysis, namely, in resistor-capacitor (RC) delay. In particular, Berkeley Short-channel IGFET Model-Common Multigate (BSIM-CMG) model is utilized. The simulation of the SRAM model is carried out in HSPICE based on 14 nm process technology. A shorted-gate (SG) mode FinFET is modeled on a silicon on insulator (SOI) substrate. It is tested in terms of functionality and stability. Then, a functional SRAM is simulated with 5 GHz square wave at the input of word line (WL). Ideal square wave and square wave with 100 RC, 5 RC, 1 RC, and 0.5 RC are asserted to the WL and the bit lines (BL&BLB) of SRAM. Voltage at node q and q - is observed. The simulation shows that 1 RC is the minimum square wave that will store correct value in node q and node q - . Thus, this discovery from the research can be used as a modeling platform for circuit designers to explore and improve the SRAM tolerance against RC delay Hindawi Publishing Corporation 2014 Article PeerReviewed application/pdf en http://eprints.utm.my/id/eprint/54446/1/WeiLim2014_Performanceevaluationof14nm.pdf Lim, Wei and Chin, Huei Chaeng and Lim, Cheng Siong and Tan, Michael Loong Peng (2014) Performance evaluation of 14nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis. Journal of Nanomaterials, 2014 . ISSN 1687-4110 http://dx.doi.org/10.1155/2014/820763 DOI: 10.1155/2014/820763
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Lim, Wei
Chin, Huei Chaeng
Lim, Cheng Siong
Tan, Michael Loong Peng
Performance evaluation of 14nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis
description As the technology node size decreases, the number of static random-access memory (SRAM) cells on a single word line increases. The coupling capacitance will increase with the increase of the load of word line, which reduces the performance of SRAM, more obvious in the SRAM signal delay and the SRAM power usage. The main purpose of this study is to investigate the stability and evaluate the power consumption of a 14 nm gate length FinFET-based 6T SRAM cell functionality for direct current (DC) and transient circuit analysis, namely, in resistor-capacitor (RC) delay. In particular, Berkeley Short-channel IGFET Model-Common Multigate (BSIM-CMG) model is utilized. The simulation of the SRAM model is carried out in HSPICE based on 14 nm process technology. A shorted-gate (SG) mode FinFET is modeled on a silicon on insulator (SOI) substrate. It is tested in terms of functionality and stability. Then, a functional SRAM is simulated with 5 GHz square wave at the input of word line (WL). Ideal square wave and square wave with 100 RC, 5 RC, 1 RC, and 0.5 RC are asserted to the WL and the bit lines (BL&BLB) of SRAM. Voltage at node q and q - is observed. The simulation shows that 1 RC is the minimum square wave that will store correct value in node q and node q - . Thus, this discovery from the research can be used as a modeling platform for circuit designers to explore and improve the SRAM tolerance against RC delay
format Article
author Lim, Wei
Chin, Huei Chaeng
Lim, Cheng Siong
Tan, Michael Loong Peng
author_facet Lim, Wei
Chin, Huei Chaeng
Lim, Cheng Siong
Tan, Michael Loong Peng
author_sort Lim, Wei
title Performance evaluation of 14nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis
title_short Performance evaluation of 14nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis
title_full Performance evaluation of 14nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis
title_fullStr Performance evaluation of 14nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis
title_full_unstemmed Performance evaluation of 14nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis
title_sort performance evaluation of 14nm finfet-based 6t sram cell functionality for dc and transient circuit analysis
publisher Hindawi Publishing Corporation
publishDate 2014
url http://eprints.utm.my/id/eprint/54446/1/WeiLim2014_Performanceevaluationof14nm.pdf
http://eprints.utm.my/id/eprint/54446/
http://dx.doi.org/10.1155/2014/820763
_version_ 1643653521507090432
score 13.211869

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