An FPGA hardware architecture of nilsimsa fingerprinting algorithm
Nilsimsa algorithm is a very effective spam fingerprinting technique. This spam fingerprinting algorithm is formulated for software implementation. In this paper, we present an FPGA hardware architecture of the modified form of Nilsimsa algorithm which has similar accurate with the original software...
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2011
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my.utm.455672017-09-20T08:23:49Z http://eprints.utm.my/id/eprint/45567/ An FPGA hardware architecture of nilsimsa fingerprinting algorithm Monemi, Alireza Mohamed, Muhidin Abdullahi Marsono, Muhammad Nadzir Nilsimsa algorithm is a very effective spam fingerprinting technique. This spam fingerprinting algorithm is formulated for software implementation. In this paper, we present an FPGA hardware architecture of the modified form of Nilsimsa algorithm which has similar accurate with the original software-targeted algorithm. The modification results in hardware resources reduction and execution time speed up. The implemented algorithm works at 123 MHz frequency and has a throughput of 1 byte per 2 clock cycles (494 Megabits per second). Our system also needs an extra 512 clock cycles after receiving the entire of the message to compute the Nilsimsa fingerprint. This means the minimum time for computing the fingerprint of a message with the size of 10 Kbytes is 167 μ s, which is equal to 5988 emails per second. For 100 MHz clock, our proposed architecture is 1400 times faster compared to implementation on 32-bit general-purpose embedded processor, and 24 times faster than the implementation on a modern CPU running on 2.64 GHz clock. 2011 Conference or Workshop Item PeerReviewed Monemi, Alireza and Mohamed, Muhidin Abdullahi and Marsono, Muhammad Nadzir (2011) An FPGA hardware architecture of nilsimsa fingerprinting algorithm. In: International Conference On Electrical, Control And Computer Engineering (INECCE 2011). http://dx.doi.org/10.1109/INECCE.2011.5953862 |
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Nilsimsa algorithm is a very effective spam fingerprinting technique. This spam fingerprinting algorithm is formulated for software implementation. In this paper, we present an FPGA hardware architecture of the modified form of Nilsimsa algorithm which has similar accurate with the original software-targeted algorithm. The modification results in hardware resources reduction and execution time speed up. The implemented algorithm works at 123 MHz frequency and has a throughput of 1 byte per 2 clock cycles (494 Megabits per second). Our system also needs an extra 512 clock cycles after receiving the entire of the message to compute the Nilsimsa fingerprint. This means the minimum time for computing the fingerprint of a message with the size of 10 Kbytes is 167 μ s, which is equal to 5988 emails per second. For 100 MHz clock, our proposed architecture is 1400 times faster compared to implementation on 32-bit general-purpose embedded processor, and 24 times faster than the implementation on a modern CPU running on 2.64 GHz clock. |
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Conference or Workshop Item |
author |
Monemi, Alireza Mohamed, Muhidin Abdullahi Marsono, Muhammad Nadzir |
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Monemi, Alireza Mohamed, Muhidin Abdullahi Marsono, Muhammad Nadzir An FPGA hardware architecture of nilsimsa fingerprinting algorithm |
author_facet |
Monemi, Alireza Mohamed, Muhidin Abdullahi Marsono, Muhammad Nadzir |
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Monemi, Alireza |
title |
An FPGA hardware architecture of nilsimsa fingerprinting algorithm |
title_short |
An FPGA hardware architecture of nilsimsa fingerprinting algorithm |
title_full |
An FPGA hardware architecture of nilsimsa fingerprinting algorithm |
title_fullStr |
An FPGA hardware architecture of nilsimsa fingerprinting algorithm |
title_full_unstemmed |
An FPGA hardware architecture of nilsimsa fingerprinting algorithm |
title_sort |
fpga hardware architecture of nilsimsa fingerprinting algorithm |
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2011 |
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http://eprints.utm.my/id/eprint/45567/ http://dx.doi.org/10.1109/INECCE.2011.5953862 |
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