AMBA AXI bus to network-on-chip bridge
Bus architectures are a neccessity for today’s System-On-Chip (SoC) design. Current SoC design is getting more complex with additional features and functions. The bus architecure arbitration need to handle requests from multiple cores where this will ultimately becomes a bottleneck to the bus archit...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/44644/5/NgKengYokeMFKE2013.pdf http://eprints.utm.my/id/eprint/44644/ |
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| Summary: | Bus architectures are a neccessity for today’s System-On-Chip (SoC) design. Current SoC design is getting more complex with additional features and functions. The bus architecure arbitration need to handle requests from multiple cores where this will ultimately becomes a bottleneck to the bus architecture performances. Most Intellectual Property (IP) designs today use bus protocol such as Advanced Microcontroller Bus Architecture (AMBA) Advanced High-performance Bus (AHB) and are facing such limitations. The ability for an IP core to be reusable in Network-on- Chip (NoC) based SoCs is highly desirable. The solution is to implement the AMBA Advanced eXtensible Interface (AXI) to NoC bridge which emulates the bus protocol and convert it to NoC protocol and vice versa, enabling quick migration of IPs cores designed for a traditional bus architecture to the NoC architecture. In this work, a busto- NoC bridge has been designed. The bus-to-NoC bridge converts the AMBA AXI bus protocol to NoC protocol and sends through NoC interface, achieving performance gain comparable to the traditional AMBA bus architectures. The advantages of busto- NoC bridge architecture includes 1. Two times performance gain in terms of latency and throughput compared to tranditional bus architectures. 2. Supports various AXI command signals such as protection unit supports information signals, Atomic operations signals, error response encoding for AXI and ordering rules signals. 3. The ability to support burst for memory access. This enables the migration of bus architectures to NoC architectures, which will likely be the future design trend. |
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