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Finite impulse response filter design on distributed arithmetic architecture

In signal and image processing application, highly repetitive operations and intense multiplication computation that exist in Digital Signal Processing systems makes it challenging to achieve less hardware requirement (area) and less latency (speed) performance using software based platforms, thus a...

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Main Author: Abu Zaharin, Muhamad Iqbal
Format: Thesis
Language:English
Published: 2012
Subjects:
TK5101-6720 Telecommunication
Online Access:http://eprints.utm.my/id/eprint/32096/5/MuhamadIqbalAbuZaharinMFKE2012.pdf
http://eprints.utm.my/id/eprint/32096/
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spelling my.utm.320962017-09-28T05:44:58Z http://eprints.utm.my/id/eprint/32096/ Finite impulse response filter design on distributed arithmetic architecture Abu Zaharin, Muhamad Iqbal TK5101-6720 Telecommunication In signal and image processing application, highly repetitive operations and intense multiplication computation that exist in Digital Signal Processing systems makes it challenging to achieve less hardware requirement (area) and less latency (speed) performance using software based platforms, thus a lot of hardware design architecture becomes available to fill the gap. A close examination of the algorithms used in these, and related, applications reveals that many of these fundamental actions involve calculation of sum of products, vector dot product, inner product or multiply and accumulate (MAC). A study on the FIR filter involves multiply and accumulates operation where inner product forms the basis of the algorithms of the core. It is the aim of this paper to develop efficient architecture of a FIR filter on Distributed Arithmetic (DA) through ROM based ideally suited for efficient computation in order to achieve better performances in terms of speed and area by providing an effective methodology to implement MAC using a simple combination of memory elements, adders and shifters instead of lumped multipliers. The design is an 8-tap low pass filter based on 16-bit input samples and 16-bit signed coefficients at sampling frequency of 16MHz. All the coefficients are stored in the ROM 8x16 words size. The behavioural model of the FIR filter is structured in Verilog code and synthesized using Altera QuartusII version 11. The timing simulation is verified by running testbench codes written in Verilog using ModelSim 6.6d. The results from the simulation show that the FIR filter can be implemented using Distributed Architecture rather than using lumped multipliers. 2012-06 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/id/eprint/32096/5/MuhamadIqbalAbuZaharinMFKE2012.pdf Abu Zaharin, Muhamad Iqbal (2012) Finite impulse response filter design on distributed arithmetic architecture. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic TK5101-6720 Telecommunication
spellingShingle TK5101-6720 Telecommunication
Abu Zaharin, Muhamad Iqbal
Finite impulse response filter design on distributed arithmetic architecture
description In signal and image processing application, highly repetitive operations and intense multiplication computation that exist in Digital Signal Processing systems makes it challenging to achieve less hardware requirement (area) and less latency (speed) performance using software based platforms, thus a lot of hardware design architecture becomes available to fill the gap. A close examination of the algorithms used in these, and related, applications reveals that many of these fundamental actions involve calculation of sum of products, vector dot product, inner product or multiply and accumulate (MAC). A study on the FIR filter involves multiply and accumulates operation where inner product forms the basis of the algorithms of the core. It is the aim of this paper to develop efficient architecture of a FIR filter on Distributed Arithmetic (DA) through ROM based ideally suited for efficient computation in order to achieve better performances in terms of speed and area by providing an effective methodology to implement MAC using a simple combination of memory elements, adders and shifters instead of lumped multipliers. The design is an 8-tap low pass filter based on 16-bit input samples and 16-bit signed coefficients at sampling frequency of 16MHz. All the coefficients are stored in the ROM 8x16 words size. The behavioural model of the FIR filter is structured in Verilog code and synthesized using Altera QuartusII version 11. The timing simulation is verified by running testbench codes written in Verilog using ModelSim 6.6d. The results from the simulation show that the FIR filter can be implemented using Distributed Architecture rather than using lumped multipliers.
format Thesis
author Abu Zaharin, Muhamad Iqbal
author_facet Abu Zaharin, Muhamad Iqbal
author_sort Abu Zaharin, Muhamad Iqbal
title Finite impulse response filter design on distributed arithmetic architecture
title_short Finite impulse response filter design on distributed arithmetic architecture
title_full Finite impulse response filter design on distributed arithmetic architecture
title_fullStr Finite impulse response filter design on distributed arithmetic architecture
title_full_unstemmed Finite impulse response filter design on distributed arithmetic architecture
title_sort finite impulse response filter design on distributed arithmetic architecture
publishDate 2012
url http://eprints.utm.my/id/eprint/32096/5/MuhamadIqbalAbuZaharinMFKE2012.pdf
http://eprints.utm.my/id/eprint/32096/
_version_ 1643648939695538176
score 13.211869

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