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Asic design of a kohonen neural network microchip

This paper discusses the Kohonen neural network (KNN) processor and its KNN computation engine microchip. The ASIC design of the KNN processor adopts a novel implementation approach whereby the computation of the KNN algorithm is performed on the custom ASIC microchip and its operations are governed...

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Main Authors: Rajah, Avinash, Hani, Mohamed Khalil
Format: Book Section
Language:English
Published: IEEE 2004
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/2031/1/RajahKhalilHani2004__ASICDesignKohonenNeuralNetwork.pdf
http://eprints.utm.my/id/eprint/2031/
http://dx.doi.org/10.1109/SMELEC.2004.1620857
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spelling my.utm.20312013-12-18T03:29:54Z http://eprints.utm.my/id/eprint/2031/ Asic design of a kohonen neural network microchip Rajah, Avinash Hani, Mohamed Khalil TK Electrical engineering. Electronics Nuclear engineering This paper discusses the Kohonen neural network (KNN) processor and its KNN computation engine microchip. The ASIC design of the KNN processor adopts a novel implementation approach whereby the computation of the KNN algorithm is performed on the custom ASIC microchip and its operations are governed by a FPGA based controller. Thus, the ASIC implementation of the KNN processor is derived through integration between a custom ASIC and FPGA. The 3.3V AMI 0.5um CO5M-D process technology was used to achieve the VLSI design of the computation engine microchip and the entire design adopted the BBX cell based methodology, which is a viable alternative to conventional ASIC methodology. IEEE 2004-12-07 Book Section PeerReviewed application/pdf en http://eprints.utm.my/id/eprint/2031/1/RajahKhalilHani2004__ASICDesignKohonenNeuralNetwork.pdf Rajah, Avinash and Hani, Mohamed Khalil (2004) Asic design of a kohonen neural network microchip. In: Proceedings ICSE 2004 - 2004 IEEE International Conference on Semiconductor Electronics. IEEE, USA, pp. 148-151. http://dx.doi.org/10.1109/SMELEC.2004.1620857 DOI:10.1109/SMELEC.2004.1620857
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Rajah, Avinash
Hani, Mohamed Khalil
Asic design of a kohonen neural network microchip
description This paper discusses the Kohonen neural network (KNN) processor and its KNN computation engine microchip. The ASIC design of the KNN processor adopts a novel implementation approach whereby the computation of the KNN algorithm is performed on the custom ASIC microchip and its operations are governed by a FPGA based controller. Thus, the ASIC implementation of the KNN processor is derived through integration between a custom ASIC and FPGA. The 3.3V AMI 0.5um CO5M-D process technology was used to achieve the VLSI design of the computation engine microchip and the entire design adopted the BBX cell based methodology, which is a viable alternative to conventional ASIC methodology.
format Book Section
author Rajah, Avinash
Hani, Mohamed Khalil
author_facet Rajah, Avinash
Hani, Mohamed Khalil
author_sort Rajah, Avinash
title Asic design of a kohonen neural network microchip
title_short Asic design of a kohonen neural network microchip
title_full Asic design of a kohonen neural network microchip
title_fullStr Asic design of a kohonen neural network microchip
title_full_unstemmed Asic design of a kohonen neural network microchip
title_sort asic design of a kohonen neural network microchip
publisher IEEE
publishDate 2004
url http://eprints.utm.my/id/eprint/2031/1/RajahKhalilHani2004__ASICDesignKohonenNeuralNetwork.pdf
http://eprints.utm.my/id/eprint/2031/
http://dx.doi.org/10.1109/SMELEC.2004.1620857
_version_ 1643643480735481856
score 13.211869

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