The performance study of two genetic algorithm approaches for VLSI macro-cell layout area optimization
Very Large Scale Integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important in order to reduce the delay and include more functionalities to the designed...
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Institute of Electrical and Electronics Engineers
2008
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my.utm.127822017-10-04T04:32:32Z http://eprints.utm.my/id/eprint/12782/ The performance study of two genetic algorithm approaches for VLSI macro-cell layout area optimization Abdul Rahim, Herlina Abdul Rahman, Azrul Azwan Ahmad, R. B. Wan Ariffin, Wan N. F. Ahmad, M.I. TK Electrical engineering. Electronics Nuclear engineering Very Large Scale Integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important in order to reduce the delay and include more functionalities to the designed chip. The VLSI cell area optimization continues to become increasingly important to the performance of VLSI design due to the accelerating of the design complexities in VLSI. Thus, this paper addresses the performance comparisons of two different types of Genetic Algorithm (GA) techniques for VLSI macrocell layout area optimization by utilizing the adopted method of cell placement that is binary tree method. Two GA approaches which are Simple Genetic Algorithm (SGA) and Steady-State Genetic Algorithm (SSGA) have been implemented and their performances in converging to their global minimums are examined and discussed. The performances of these techniques are tested on Microelectronics Center of North Carolina (MCNC) benchmark circuit's data set. The experimental results demonstrate that both algorithms achieve acceptable area requirement compared to the slicing floorplan approach [1]. However, SSGA outperforms SGA where it achieves faster convergence rate and obtains more near optimum area. Institute of Electrical and Electronics Engineers 2008 Book Section PeerReviewed Abdul Rahim, Herlina and Abdul Rahman, Azrul Azwan and Ahmad, R. B. and Wan Ariffin, Wan N. F. and Ahmad, M.I. (2008) The performance study of two genetic algorithm approaches for VLSI macro-cell layout area optimization. In: Proceedings - 2nd Asia International Conference on Modelling and Simulation, AMS 2008. Institute of Electrical and Electronics Engineers, New York, pp. 207-212. ISBN 978-076953136-6 http://dx.doi.org/10.1109/AMS.2008.117 doi:10.1109/AMS.2008.117 |
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TK Electrical engineering. Electronics Nuclear engineering Abdul Rahim, Herlina Abdul Rahman, Azrul Azwan Ahmad, R. B. Wan Ariffin, Wan N. F. Ahmad, M.I. The performance study of two genetic algorithm approaches for VLSI macro-cell layout area optimization |
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Very Large Scale Integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important in order to reduce the delay and include more functionalities to the designed chip. The VLSI cell area optimization continues to become increasingly important to the performance of VLSI design due to the accelerating of the design complexities in VLSI. Thus, this paper addresses the performance comparisons of two different types of Genetic Algorithm (GA) techniques for VLSI macrocell layout area optimization by utilizing the adopted method of cell placement that is binary tree method. Two GA approaches which are Simple Genetic Algorithm (SGA) and Steady-State Genetic Algorithm (SSGA) have been implemented and their performances in converging to their global minimums are examined and discussed. The performances of these techniques are tested on Microelectronics Center of North Carolina (MCNC) benchmark circuit's data set. The experimental results demonstrate that both algorithms achieve acceptable area requirement compared to the slicing floorplan approach [1]. However, SSGA outperforms SGA where it achieves faster convergence rate and obtains more near optimum area. |
| format |
Book Section |
| author |
Abdul Rahim, Herlina Abdul Rahman, Azrul Azwan Ahmad, R. B. Wan Ariffin, Wan N. F. Ahmad, M.I. |
| author_facet |
Abdul Rahim, Herlina Abdul Rahman, Azrul Azwan Ahmad, R. B. Wan Ariffin, Wan N. F. Ahmad, M.I. |
| author_sort |
Abdul Rahim, Herlina |
| title |
The performance study of two genetic algorithm approaches for VLSI macro-cell layout area optimization |
| title_short |
The performance study of two genetic algorithm approaches for VLSI macro-cell layout area optimization |
| title_full |
The performance study of two genetic algorithm approaches for VLSI macro-cell layout area optimization |
| title_fullStr |
The performance study of two genetic algorithm approaches for VLSI macro-cell layout area optimization |
| title_full_unstemmed |
The performance study of two genetic algorithm approaches for VLSI macro-cell layout area optimization |
| title_sort |
performance study of two genetic algorithm approaches for vlsi macro-cell layout area optimization |
| publisher |
Institute of Electrical and Electronics Engineers |
| publishDate |
2008 |
| url |
http://eprints.utm.my/id/eprint/12782/ http://dx.doi.org/10.1109/AMS.2008.117 |
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1643646040656576512 |
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13.211869 |